el4585 Intersil Corporation, el4585 Datasheet - Page 8

• Manufacturer Part Number: el4585
• Description: Horizontal Genlock, 8fsc
• Manufacturer: Intersil Corporation

values to use for any given situation. Use the component
tables as a starting point, but be aware that deviations from
these values are not out of the ordinary.
External Divide
DIV SEL (pin 8) controls the use of the internal divider. When
high, the internal divider is enabled and EXT DIV (pin 13)
outputs the CLK out divided by 2N. This is the signal to
which the horizontal sync input will lock. When divide select
is low, the internal divider output is disabled, and external
divide becomes an input from an external divider, so that a
divisor other than one of the 8 pre-programmed internal
divisors can be used.
Normal Mode
Normal mode is enabled by pulling COAST (pin 9) low
(below 1/3*V
frequency difference, an error signal is generated and sent
to the charge pump. The charge pump will either force
current into or out of the filter capacitor in an attempt to
modulate the VCO frequency. Modulation will continue until
the phase and frequency of CLK ÷ 2N exactly match the
H
some offset in phase that is a function of the VCO
characteristics), the error signal goes to zero, lock detect no
longer pulses high, and the charge pump enters a high
impedance state. The clock is now locked to the H
input. As long as phase and frequency differences remain
small, the PLL can adjust the VCO to remain locked and lock
detect remains low.
Fast Lock Mode
Fast Lock mode is enabled by either allowing coast to float,
or pulling it to mid supply (between 1/3 and 2/3*V
mode, lock is achieved much faster than in normal mode, but
the clock divisor is modified on the fly to achieve this. If the
phase detector detects an error of enough magnitude, the
clock is either inhibited or reset to attempt a “fast lock” of the
signals. Forcing the clock to be synchronized to the H
input this way allows a lock in approximately 2 H-cycles, but
the clock spacing will not be regular during this time. Once
the near lock condition is attained, charge pump output
should be very close to its lock-on value, and placing the
device into normal mode should result in a normal lock very
quickly. Fast lock mode is intended to be used where H
becomes irregular, until a stable signal is again obtained.
Coast Mode
Coast mode is enabled by pulling COAST (pin 9) high
(above 2/3*V
is disabled and filter out remains in high impedance mode to
keep filter out voltage and VCO frequency as constant as
possible. VCO frequency will drift as charge leaks from the
filter capacitor, and the voltage changes the VCO operating
point. Coast mode is intended to be used when noise or
signal degradation result in loss of horizontal sync for many
cycles. The phase detector will not attempt to adjust to the
SYNC
input. When the phase and frequency match (with
CC
CC
). If H
). In coast mode the internal phase detector
SYNC
and CLK ÷ 2N have any phase or
8
CC
SYNC
). In this
SYNC
SYNC
EL4585
resultant loss of signal so that when horizontal sync returns,
sync lock can be re-established quickly. However, if much
VCO drift has occurred, it may take as long to re-lock as
when restarting.
Lock Detect
Lock detect (pin 12) will go low when lock is established. Any
DC current path from charge pump out will skew EXT DIV
relative to H
internal delay, depending on which way the extra current is
flowing. This offset is called static phase error, and is always
present in any PLL system. If, when the part stabilizes in a
locked mode, lock detect is not low, adding or subtracting
from the loop filter series resistor R
phase error to allow LDET to go low while in lock. The goal is
to put the rising edge of EXT DIV in sync with the falling
edge of H
R
phase error. (Phase error is positive when EXT DIV lags
H
or VCXO module selection.
Applications Information
Choosing External Components
F
C
C
then:
C
1. To choose LC VCO components, first pick the desired
2. Choose a reasonable inductor value (1-5µH works well).
3. Calculate C
4. From the varactor data sheet find C
5. C
6. Calculate C
OSC
T
T
1
2
SYNC
decreases phase error, while decreasing R
=
=
=
operating frequency. For our example we will use
28.636MHz, with an H
We choose 3.3µH.
lock voltage. C
our example.
2
------------------------------------------------------------------------- -
(
-------------------- -
4π
------------------------------------------------------------------------- -
(
=
C
C
.) The resistance needed will depend on VCO design
should be about 10C
2
2
1
---------------------- -
2π LC
1
C
C
F
SYNC
2
V
2
L
1
)
SYNC
)
+
–
=
C
C
(
(
T
C
C
T
1
2
1
+ 110ns. (See timing diagrams.) Increasing
---------------------------------------------------------------------- -
4π
. Since:
C
C
2
1
needed to produce F
C
C
in, tending to offset or add to the 110ns
T
2
2
V
C
C
V
T
(
=23pF for our SMV1204-12 for example.
28.636e6
)
)
V
V
–
+
(
(
C
C
T
SYNC
2
C
C
1
V
V
V
2
, so we choose C
)
)
) 3.3e 6
(
frequency of 15.734kHz.
2
–
will change this static
OSC
V
)
@ 2.5V, the desired
=
.
9.4pF
2
2
=220pF for
increases
July 1, 2005
FN7175.3