el4585 Intersil Corporation, el4585 Datasheet

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el4585

Manufacturer Part Number
el4585
Description
Horizontal Genlock, 8fsc
Manufacturer
Intersil Corporation
Datasheet

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Horizontal Genlock, 8F
The EL4585 is a PLL (Phase Lock Loop) sub-system,
designed for video applications and also suitable for general
purpose use up to 36MHz. In video applications, this device
generates a TTL/CMOS-compatible pixel clock (CLK OUT)
which is a multiple of the TV horizontal scan rate and phase
locked to it.
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog
composite video signal with the EL4583 sync separator. An
input signal to “coast” is provided for applications where
periodic disturbances are present in the reference video
timing such as VTR head switching. The lock detector output
indicates correct lock.
The divider ratio is four ratios for NTSC and four similar
ratios for the PAL video timing standards by external
selection of three control pins. These four ratios have been
selected for common video applications including 8F
6F
elements used in some workstation graphics. To generate
4F
EL4584, which does not have the additional divide-by-two
stage of the EL4585.
For applications where these frequencies are inappropriate
or for general purpose PLL applications the internal divider
can be bypassed and an external divider chain used.
NOTES:
Divisor (Note 4)
PAL F
Divisor (Note 4)
NTSC F
1. 6F
2. CCIR 601 divisors yield 1440 pixels in the active portion of each
3. Square pixels format gives 640 pixels for NTSC and 768 pixels
4. Divisor does not include ÷ 2 block.
SC
SC
line for NTSC and PAL.
for PAL.
FUNCTION
, 27MHz (CCIR 601 format) and square picture
, 3F
SC
OSC
OSC
frequencies do not yield integer divisors.
SC
(MHz)
, 13.5MHz (CCIR 601 format) etc., use the
(MHz)
FREQUENCIES AND DIVISORS
(NOTE 1)
26.602
21.476
6F
1702
1364
SC
®
CCIR 601
1
(NOTE 2)
1728
1716
27.0
27.0
SC
Data Sheet
SQUARE
(NOTE 3)
24.546
1888
1560
29.5
35.468
28.636
SC
8F
2270
1820
1-888-INTERSIL or 1-888-352-6832
SC
,
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• 36MHz, general purpose PLL
• 8F
• Compatible with EL4583 sync separator
• VCXO, Xtal, or LC tank oscillator
• < 2ns jitter (VCXO)
• User-controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed popular TV scan rate clock divisors
• Single 5V, low current operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Pixel clock regeneration
• Video compression engine (MPEG) clock generator
• Video capture or digitization
• PIP (Picture in Picture) timing generator
• Text or graphics overlay timing
Ordering Information
*For 3F
datasheet.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
EL4585CN
EL4585CS
EL4585CS-T7
EL4585CS-T13
EL4585CSZ
(See Note)
EL4585CSZ-T7
(See Note)
EL4585CSZ-T13
(See Note)
NUMBER
SC
PART
SC
timing (use the EL4584 for 4F
All other trademarks mentioned are the property of their respective owners.
and 4F
|
July 1, 2005
Intersil (and design) is a registered trademark of Intersil Americas Inc.
SC
Copyright Intersil Americas Inc. 2003-2005. All Rights Reserved
16-Pin SO (0.150”)
16-Pin SO (0.150”)
16-Pin SO (0.150”)
16-Pin SO (0.150”)
16-Pin SO (0.150”)
16-Pin SO (0.150”)
clock frequency operation, see EL4584
16-Pin PDIP
PACKAGE
(Pb-free)
(Pb-free)
(Pb-free)
TAPE &
SC
REEL
13”
13”
7”
7”
-
-
-
)
EL4585
FN7175.3
PKG. DWG.
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
#

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el4585 Summary of contents

Page 1

... Data Sheet Horizontal Genlock The EL4585 is a PLL (Phase Lock Loop) sub-system, designed for video applications and also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to it ...

Page 2

... Demo Board A demo PCB is available for this product. Pinout EL4585 (16-PIN SO, PDIP) TOP VIEW 2 EL4585 FN7175.3 July 1, 2005 ...

Page 3

... OL = -1.6mA OH = 3.2mA OL = -3.2mA OH = 200µ -200µ 2.5V OUT = 2.5V OUT = 2.5V OUT > V > OUT = 5V 25°C unless otherwise noted DD A Conditions input to EL4585. Test for positive signal lock. SYNC Min Typ Max UniT 1.5 V 3.5 V -100 nA 100 nA -100 -60 µA 60 100 µA 0.4 V 2.4 V ...

Page 4

... EL4585 Digital inputs to select ÷ N value for internal counter. See Table 1 for values. Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit. Analog positive supply for oscillator, PLL circuits. Input from external VCO. Analog ground for oscillator, PLL circuits. ...

Page 5

... Timing Diagrams Test Circuit 5 EL4585 PLL LOCKED CONDITION (PHASE ERROR = 0) OUT OF LOCK CONDITION TEST CIRCUIT 1 θ × 360° = Tθ period H YNC Tθ = phase error period FN7175.3 July 1, 2005 ...

Page 6

... PDIP16 1 0.91W θ JA 0.8 0.6 SO16 (0.150”) θ 0.4 =110°C AMBIENT TEMPERATURE (°C) 6 EL4585 OSC GAIN vs F OSC Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 2 1.8 1.6 1.43W 1.4 1.25W 1.2 =81°C/W 1 0.8 0.6 0.4 0 100 125 150 ...

Page 7

... The clock is generated by the signal on pin 5, OSC IN. There are 2 general types of VCO that can be used with the EL4585, LC and crystal controlled. Additionally, each type can be either built up using discrete components, including a varactor as the frequency controlling element, or complete, self contained modules can be purchased with everything inside a metal can ...

Page 8

... The phase detector will not attempt to adjust to the 8 EL4585 resultant loss of signal so that when horizontal sync returns, sync lock can be re-established quickly. However, if much VCO drift has occurred, it may take as long to re-lock as when restarting ...

Page 9

... NOTE: Use shielded inductors for optimum performance. TYPICAL XTAL VCO 9 EL4585 Typical Application Horizontal genlock provides clock for an analog to digital converter, digitizing analog video. (pF) C (pF) FREQUENCY 2 (MHz) 220 26.602 220 220 220 35.468 220 21.476 220 24 ...

Page 10

... Where ω = loop filter bandwidth, and ζ = loop filter damping n factor 300µA/2πrad = 4.77e-5A/rad for the EL4585 The loop bandwidth should be about H frequency/20, and the damping ratio should be 1 for optimum performance. For our example, ω = 15.734kHz/20=787 Hz≈5000 rad/S. ...

Page 11

... EL4585/4 Demo Board 11 EL4585 PCB Layout Considerations It is highly recommended that power and ground planes be used in layout. The oscillator and filter sections constitute a C (µF) C (µF) feedback loop and thus care must be taken to avoid any ...

Page 12

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 EL4585 (2) XTAL • SaRonix 151 Laura Lane ...

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