adf4218l Analog Devices, Inc., adf4218l Datasheet - Page 3

• Manufacturer Part Number: adf4218l
• Description: Dual Low Power Frequency Synthesizers
• Manufacturer: Analog Devices, Inc.

Parameter
NOISE CHARACTERISTICS
NOTES
10
11
12
Specifications subject to change without notice.
REV. C
TIMING CHARACTERISTICS
V
Parameter
t
t
t
t
t
t
Guaranteed by design but not production tested.
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
for the synthesizer. (f
f
f
f
P
Operating temperature range is as follows: B Version: –40°C to +85°C.
The BChip specifications are given as typical values.
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
Guaranteed by design. Sample tested to ensure compliance.
This includes relevant I
V
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
The phase noise is measured with the EVAL-ADF421xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN
f
that is less than this value.
REFIN
REFIN
REFIN
REFIN
RF Phase Noise Floor
IF Phase Noise Floor
Phase Noise Performance
Spurious Signals
2 ≤ 6.0 V ; AGND
DD
RF
RF
IF
IF
RF
RF
IF
IF
= 3 V; P = 16/32; IF
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
11
12
11
12
9
10
9
10
CLOCK
PFD
PFD
PFD
PFD
RF1
DATA
REFOUT
= 30 kHz; Offset frequency = 1 kHz; f
= 200 kHz; Offset frequency = 1 kHz; f
= 30 kHz; Offset frequency = 1 kHz; f
= 200 kHz; Offset frequency = 1 kHz; f
LE
LE
= DGND
P
.
IN
Limit at
T
(B Version)
10
10
25
25
10
50
MIN
/RF
7
= 10 MHz @ 0 dBm.)
7
DB21 (MSB)
IN
RF1
to T
8
for ADF4218L, ADF4219L = 540 MHz/900 MHz.
= AGND
6
MAX
RF2
= DGND
t
1
(V
ns min
ns min
ns min
ns min
ns min
ns min
Unit
DD
DB20
1 = V
B Version
–171
–163
–167
–159
–75
–90
–77
–86
–78/–85
–80/–84
–79/–86
–80/–84
RF2
IF
RF
t
= 0 V; T
2
RF
IF
DD
= 900 MHz; N = 30000; Loop B/W = 3 kHz
= 1.95 GHz; N = 65000; Loop B/W = 3 kHz
Figure 1. Timing Diagram
= 900 MHz; N = 4500; Loop B/W = 20 kHz
2 = 3 V
= 900 MHz; N = 4500; Loop B/W = 20 kHz
A
1
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
= T
MIN
DB2
BChips
(Typical)
–171
–163
–167
–159
–75
–90
–77
–86
–78/–85
–80/–84
–79/–86
–80/–84
10%, 5 V
–3–
to T
t
3
MAX
2
, unless otherwise noted.)
t
10%; V
(CONTROL BIT C2)
4
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Unit
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc typ
dBc typ
dBc typ
dBc typ
DB1
DD
1, V
ADF4217L/ADF4218L/ADF4219L
DD
2 ≤ V
P
1,
Test Conditions/Comments
@ 30 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 30 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
1.95 GHz Output; 30 kHz PFD
900 MHz Output; 200 kHz PFD
900 MHz Output; 30 kHz PFD
900 MHz Output; 200 kHz PFD
Measured at Offset of f
(CONTROL BIT C1)
t
5
DB0 (LSB)
t
6
PFD
/2f
PFD