adf4218l Analog Devices, Inc., adf4218l Datasheet - Page 21

• Manufacturer Part Number: adf4218l
• Description: Dual Low Power Frequency Synthesizers
• Manufacturer: Analog Devices, Inc.

In this circuit, the reference input signal is applied to the circuit
at REF
oscillator).
INTERFACING
The ADF4217L/ADF4218L/ADF4219L family has a simple
SPI
SDATA, and LE control the data transfer. When LE (latch
enable) goes high, the 22 bits that have been clocked into the
input register on each rising edge of SCLK will get transferred
to the appropriate latch. See Figure 1 for the timing diagram
and Table I for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 909 kHz
or one update every 1.1 µs. This is certainly more than adequate
for systems that will have typical lock times in hundreds of
microseconds.
ADuC812 Interface
Figure 9 shows the interface to the ADuC812 MicroConverter
Since the ADuC812 is based on an 8051 core, this interface can
be used with any 8051 based microcontroller. The MicroConverter
is set up for SPI Master Mode with CPHA = 0. To initiate the
operation, the I/O port driving LE is brought low. Each latch of
the ADF421xL family needs a 22-bit word. This is accomplished
by writing three 8-bit bytes from the MicroConverter to the
device. When the third byte has been written, the LE input should
be brought high to complete the transfer.
On first applying power to the ADF4217L family, it needs four
writes (one each to the R counter latch and the AB counter latch
for both RF1 and RF2 side) for the output to become active.
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be about
180 kHz.
REV. C
100pF
®
18
18
compatible serial interface for writing to the device. SCLK,
IF
OUT
IN
by a 10 MHz TCXO (temperature controlled crystal
18
51
100pF
DECOUPLING CAPACITORS (22 F/10pF) ON V
THE TCXO AND ON V
VCO190-200T
100pF
V
CC
10MHz
TCXO
450pF
CC
Figure 8. Local Oscillator Design for WCDMA System
OF THE VCOs HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
3.3k
1.5k
24nF
2.4pF
DD
, V
CP
IF
REF
P
V
V
IN
OF THE ADF4217L/ADF4218L/ADF4219L.
P
IF
P
2
IN
ADF4217L/
ADF4218L/
ADF4219L
®
.
V
V
DD
–21–
DD
2 V
ADSP2181 Interface
Figure 10 shows the interface between the ADF4217L family and
the ADSP-21xx digital signal processor. As previously discussed,
the ADF4217L family needs a 22-bit serial word for each latch
write. The easiest way to accomplish this using the ADSP-21xx
family is to use the autobuffered transmit mode of operation
with alternate framing. This provides a means for transmitting
an entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory loca-
tions for each 22-bit word. To program each 22-bit latch, store
the three 8-bit bytes, enable the Autobuffered Mode, and then
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
DD
1
MUXOUT
CP
DATA
V
RF
CLK
V
P
P
LE
RF
1
IN
Figure 10. ADSP-21xx to ADF421xL Interface
Figure 9. ADuC812 to ADF421xL Interface
ADF4217L/ADF4218L/ADF4219L
760pF
SPI COMPATIBLE SERIAL BUS
ADuC812
LOCK
DETECT
ADSP-21xx
I/O PORTS
I/O FLAG
SCLK
SCLK
MOSI
4.7k
TFS
7.5nF
3.3k
DT
690pF
100pF
VCO190-1750T
CLK
DATA
LE
MUXOUT
(LOCK DETECT)
CLK
DATA
LE
MUXOUT
(LOCK DETECT)
V
CC
ADF4217L/
ADF4218L/
ADF4219L
ADF4217L/
ADF4218L/
ADF4219L
51
100pF
100pF
18
RF
OUT
18
18