adf4212l Analog Devices, Inc., adf4212l Datasheet - Page 3

• Manufacturer Part Number: adf4212l
• Description: Dual Low Power Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

SPECIFICATIONS
T
Parameter
NOISE CHARACTERISTICS
NOTES
1
2
3
4
5
6
7
8
9
Specifications subject to change without notice.
TIMING CHARACTERISTICS*
Parameter
t
t
t
t
t
t
*Guaranteed by design but not production tested.
Specifications subject to change without notice.
REV. A
Operating temperature range is as follows: B Version: –40°C to +85°C
The B Chip specifications are given as typical values.
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider
The phase noise is measured with the EVAL-ADF4210/12/13EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the
f
f
Same conditions as listed on the preceding line.
f
f
value). See TPC 14.
REFIN for the synthesizer (f
1
2
3
4
5
6
MIN
REFIN
REFIN
REFIN
REFIN
RF Phase Noise Floor
Phase Noise Performance
Spurious Signals
to T
IF: 540 MHz Output
IF: 900 MHz Output
RF: 900 MHz Output
RF: 1750 MHz Output
RF: 2400 MHz Output
IF: 540 MHz Output
IF: 900 MHz Output
RF: 900 MHz Output
RF: 1750 MHz Output
RF: 2400 MHz Output
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
MAX
, unless otherwise noted; dBm referred to 50 V.)
PFD
PFD
PFD
PFD
= 200 kHz; Offset Frequency = 1 kHz; f
= 200 kHz; Offset Frequency = 1 kHz; f
= 200 kHz; Offset Frequency = 1 kHz; f
= 1 MHz; Offset Frequency = 1 kHz; f
3
REFOUT
5
6
5
6
6
6
Limit at
T
(B Version)
10
10
25
25
10
20
4
8
9
8
9
CLOCK
MIN
DATA
= 10 MHz @ 0 dBm).
LE
LE
to T
1
DB20 (MSB)
MAX
(V
B Version
–170
–162
–89
–87
–89
–84
–87
–88/–90
–90/–94
–90/–94
–80/–82
–80/–82
DD
1 = V
(V
T
A
DD
DD
= T
1 = V
2 = 2.7 V to 3.3 V; V
t
MIN
1
RF
DB19
IF
RF
RF
to T
DD
B Chips
= 2400 MHz; N = 9800; Loop B/W = 20 kHz
–170
–162
–89
–87
–89
–84
–87
–88/–90
–90/–94
–90/–94
–80/–82
–80/–82
Figure 1. Timing Diagram
= 540 MHz; N = 2700; Loop B/W = 20 kHz
= 900 MHz; N = 4500; Loop B/W = 20 kHz
= 1750 MHz; N = 8750; Loop B/W = 20 kHz
2 = 2.6 V to 3.3 V; V
Unit
ns min
ns min
ns min
ns min
ns min
ns min
t
2
MAX
, unless otherwise noted; dBm referred to 50
2
DB2
–3–
P
t
1, V
3
Unit
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dB typ
dB typ
dB typ
dB typ
dB typ
P
2 = V
P
t
(CONTROL BIT C2)
1, V
4
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
DD
P
DB1
2 = V
to 5.5 V; AGND
DD
Test Conditions/Comments
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
@ 1 kHz Offset and 200 kHz PFD Frequency
See Note 7
See Note 7
See Note 7
@ 1 kHz Offset and 1 MHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
See Note 7
See Note 7
See Note 7
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
to 5.5 V; AGND
(CONTROL BIT C1)
t
5
DB0 (LSB)
RF
= DGND
RF
= DGND
RF
.)
= AGND
t
6
RF
= AGND
IF
= DGND
IF
ADF4212L
= DGND
IF
= 0 V; T
IF
= 0 V;
A
=