adf4212l Analog Devices, Inc., adf4212l Datasheet - Page 16

• Manufacturer Part Number: adf4212l
• Description: Dual Low Power Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

ADF4212L
PROGRAM MODES
Table III and Table V show how to set up the Program Modes
in the ADF4212L. The following should be noted:
1. IF and RF Analog Lock Detect indicate when the PLL is in
2. The IF Counter Reset Mode resets the R and AB counters in
3. The Fastlock Mode uses MUXOUT to switch a second loop
IF and RF Power-Down
It is possible to program the ADF4210 family for either synchro-
nous or asynchronous power-down on either the IF or RF side.
Synchronous IF Power-Down
Programming a “1” to P7 of the ADF4212L will initiate a
power-down. If P2 of the ADF4212L has been set to “0” (nor-
mal operation), a synchronous power-down is conducted. The
device will automatically put the charge pump into three-state
and complete the power-down.
Asynchronous IF Power-Down
If P2 of the ADF4212L has been set to “1” (three-state the IF
charge pump) and P7 is subsequently set to “1,” an asynchronous
power-down is conducted. The device will go into power-down
on the rising edge of LE, which latches the “1” to the IF Power-
Down Bit (P7).
Synchronous RF Power-Down
Programming a “1” to P16 of the ADF4212L will initiate a
power-down. If P10 of the ADF4212L has been set to “0”
(normal operation), a synchronous power-down is conducted.
The device will automatically put the charge pump into three-
state and then complete the power-down.
Asynchronous RF Power-Down
If P10 of the ADF4212L has been set to “1” (three-state the RF
charge pump) and P16 is subsequently set to “1,” an asynchronous
power-down is conducted. The device will go into power-down
on the rising edge of LE, which latches the “1” to the RF Power-
Down Bit (P16).
Activation of either synchronous or asynchronous power-down
forces the IF/RF loop’s R and AB dividers to their load state
conditions and the IF/RF input section is debiased to a high
impedance state.
lock. When the loop is locked and either IF or RF Analog
Lock Detect is selected, then the MUXOUT pin will show a
logic high with narrow, low-going pulses. When the IF/RF
Analog Lock Detect is chosen, then the locked condition is
indicated only when both IF and RF loops are locked.
the IF section and also puts the IF charge pump into three-
state. The RF Counter Reset Mode resets the R and AB
counters in the RF section and also puts the RF charge
pump into three-state. The IF and RF Counter Reset Mode
does both of the above. Upon removal of the reset bits, the
AB counter resumes counting in close alignment with the R
counter. (Maximum error is one prescaler output cycle.)
filter damping resistor to ground during Fastlock operation.
Activation of Fastlock occurs whenever RF CP Gain in the
RF Reference counter is set to “1.”
–16–
The REFIN oscillator circuit is only disabled if both the IF and
RF power-downs are set.
The input register and latches remain active and are capable of
loading and latching data during all power-down modes.
The IF/RF section of the device will return to normal powered-up
operation immediately upon LE latching a “0” to the appropri-
ate Power-Down Bit.
IF SECTION
Programmable if Reference (R) Counter
If control bits C2, C1 are 0, 0, the data is transferred from the
input shift register to the 14-bit IFR counter. Table III shows
the input shift register data format for the IFR counter and the
divide ratios possible.
IF Phase Detector Polarity
P1 sets the IF Phase Detector Polarity. When the IF VCO char-
acteristics are positive, this should be set to “1.” When they are
negative, it should be set to “0.” See Table III.
IF Charge Pump Three-State
P2 puts the IF charge pump into three-state mode when pro-
grammed to a “1.” It should be set to “0” for normal operation.
See Table III.
IF Program Modes
Table III and Table V show how to set up the Program Modes
in the ADF4212L.
IF Charge Pump Currents
IFCP2, IFCP1, IFCP0 program Current Setting for the IF charge
pump. See Table III.
Programmable IF AB Counter
If control bits C2, C1 are 0, 1, the data in the input register is
used to program the IF AB counter. The N counter consists of a
6-bit swallow counter (A counter) and 12-bit programmable
counter (B counter). Table IV shows the input register data
format for programming the IF AB counter and the divide ratios
possible.
IF Prescaler Value
P5 and P6 in the IF A, B Counter Latch set the IF prescaler
values. See Table IV.
IF Power-Down
Table III and Table V show the power-down bits in the
ADF4212L.
IF Fastlock
The IF CP Gain Bit (P8) of the IF N Register in the ADF4212L
is the Fastlock Enable Bit. Only when this is “1” is IF Fastlock
enabled. When Fastlock is enabled, the IF CP current is set to
maximum value. Also, an extra loop filter damping resistor to
ground is switched in using the FLO pin, thus compensating for
the change in loop characteristics while in Fastlock. Since the IF
CP Gain Bit is contained in the IF N Counter, only one write is
needed to both program a new output frequency and initiate
Fastlock. To come out of fastlock, the IF CP Gain Bit on the IF
N Register must be set to “0.” See Table IV.
REV. A