adf4212l Analog Devices, Inc., adf4212l Datasheet - Page 17

• Manufacturer Part Number: adf4212l
• Description: Dual Low Power Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

RF SECTION
Programmable RF Reference (R) Counter
If control bits C2, C1 are 1, 0, the data is transferred from the
input shift register to the 14-bit RFR counter. Table V shows
the input shift register data format for the RFR counter and the
divide ratios possible.
RF Phase Detector Polarity
P9 sets the IF Phase Detector Polarity. When the RF VCO
characteristics are positive, this should be set to “1.” When they
are negative, it should be set to “0.” See Table V.
RF Charge Pump Three-State
P10 puts the RF charge pump into three-state mode when pro-
grammed to a “1.” It should be set to “0” for normal operation.
See Table V.
RF Program Modes
Table III and Table V show how to set up the Program Modes
in the ADF4212L.
RF Charge Pump Currents
RFCP2, RFCP1, and RFCP0 program Current Setting for the
RF charge pump. See Table V.
Programmable RF N Counter
If control bits C2, C1 are 1, 1, the data in the input register is
used to program the RF N (A + B) counter. The N counter
consists of a 6-bit swallow counter (A counter) and 12-bit pro-
grammable counter (B counter). Table IV shows the input
register data format for programming the RF N counter and the
divide ratios possible. See Table VI.
RF Prescaler Value
P14 and P15 in the RF A, B Counter Latch set the RF prescaler
values. See Table VI.
REV. A
100pF
18
18
IF
OUT
18
51
100pF
DECOUPLING CAPACITORS (22 F/10pF) ON V
HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
VCO190-540T
100pF
V
CC
Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4212L
1.3nF
FREF
IN
3.3k
1.7k
13nF
100pF
51
2.7k
100pF
620pF
DD
, V
CP
IF
REF
R
P
V
SET
IN
V
OF THE ADF4212L AND ON V
P
IF
P
2
IN
ADF4212L
V
V
–17–
DD
DD
2 V
RF Power-Down
Table III and Table V show the power-down bits in the
ADF4210 family.
RF Fastlock
The RF CP Gain Bit (P17) of the RF N Register in the
ADF4212L is the Fastlock Enable Bit. Only when this is “1” is
IF Fastlock enabled. When Fastlock is enabled, the RF CP
current is set to maximum value. Also, an extra loop filter
damping resistor to ground is switched in using the FLO pin,
thus compensating for the change in loop characteristics while
in Fastlock. Since the RF CP Gain Bit is contained in the RF N
counter, only one write is needed to both program a new output
frequency and initiate Fastlock. To come out of Fastlock, the RF
CP Gain Bit on the RF N Register must be set to “0.” See
Table VI.
APPLICATIONS
Local Oscillator for GSM Handset Receiver
Figure 7 shows the ADF4212L being used with a VCO to pro-
duce the required LOs for a GSM base station transmitter or
receiver. The reference input signal is applied to the circuit at
FREF
systems would have a 13 MHz TCXO driving the Reference
Input without any 50 Ω termination. In order to have a channel
spacing of 200 kHz (the GSM standard), the reference input
must be divided by 65, using the on-chip reference.
The RF output frequency range is 880 MHz to 915 MHz. The
loop filter is designed to give a 20 kHz loop bandwidth. The
filter is set up for a 5 mA charge pump current, and the VCO
sensitivity is 12 MHz/V. The IF output is fixed at 540 MHz.
The filter is again designed to have a bandwidth of 20 kHz, and
the system is programmed to give channel steps of 200 kHz.
DD
1
MUXOUT
CP
DATA
V
RF
CLK
V
IN
P
P
LE
1
RF
IN
and, in this case, is terminated in 50 Ω. Typical GSM
CC
SPI COMPATIBLE SERIAL BUS
1nF
LOCK
DETECT
OF THE VCOs
5.6k
8.2nF
3.3k
620pF
100pF
VCO190-902U
V
CC
ADF4212L
51
100pF
100pF
18
RF
OUT
18
18