adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 6

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

ADF4196
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Mnemonic
CMR
A
SW3
A
RF
RF
AV
DV
D
DV
REF
D
DV
SD
SDV
MUX
CLK
DATA
LE
V
D
A
P
OUT
GND
GND
GND
GND
GND
1
IN−
IN+
DD
GND
DD
DD
DD
IN
DD
1
1
2
3
2
1
2
3
OUT
Description
Common-Mode Reference Voltage for the Output Voltage Swing of the Differential Amplifier. Internally biased to
three-fifths of V
Differential Amplifier Output. This pin is the differential amplifier output to tune the external VCO.
Fast Lock Switch 3. This switch is closed when the SW3 timeout counter is active.
Analog Ground. This is the ground return pin for the differential amplifier and the RF section.
Complementary Input to the RF Prescaler. This pin must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
Input to the RF Prescaler. This small-signal input is ac-coupled to the external VCO.
Power Supply Pin for the RF Section. Nominally 3 V. Place a 100 pF decoupling capacitor to the ground plane as
close as possible to this pin.
Power Supply Pin for the N Divider. DV
capacitor to the ground plane as close as possible to this pin.
Ground Return Pin for DV
Power Supply Pin for the REF
ground plane as close as possible to this pin.
Reference Input. This CMOS input has a nominal threshold of V
This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Ground Return Pin for DV
Power Supply Pin for the Serial Interface Logic. Nominally 3 V.
Ground Return Pin for the Digital Σ-Δ Modulator.
Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the ground
plane as close as possible to this pin.
Multiplexer Output. This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally (see Figure 35 for details).
Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is
selected by the three LSBs.
Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, V
Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin.
Ground Return Pin for V
Ground Return Pin for V
P
3. Requires a 0.1 µF capacitor to the ground plane.
P
P
A
DV
NOTES
1. THE EXPOSED PADDLE MUST BE CONNECTED
1.
2.
RF
RF
AV
A
GND
DD
DD
CMR
SW3
TO THE GROUND PLANE.
OUT
DD
IN–
IN+
DD
1.
2 and DV
1
1
IN
1
2
3
4
5
6
7
8
Buffer and R Divider. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the
Figure 3. Pin Configuration
DD
PIN 1
INDICATOR
Rev. B | Page 6 of 28
(Not to Scale)
DD
3.
ADF4196
TOP VIEW
1 should be at the same voltage as AV
24
23
22
21
20
19
18
17
V
R
A
D
V
LE
DATA
CLK
P
P
SET
GND
GND
2
1
2
3
DD
/2 and a dc equivalent input resistance of 100 kΩ.
P
1 should be at the same voltage as V
DD
. Place a 0.1 µF decoupling
Data Sheet
P
2.