adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 27

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

Data Sheet
INTERFACING
The
writing to the device. The CLK, DATA, and LE pins control the
data transfer. When LE goes high, the 24 bits that have been
clocked into the input register on each rising edge of CLK are
latched into the appropriate register. See Figure 2 for the timing
diagram and Table 6 for the register address table.
The maximum allowable serial clock rate is 33 MHz.
ADuC70xx Interface
Figure 38 shows the interface between the
ADuC70xx
family is based on an ARM7™ core, although the same interface
can be used with any 8051-based microcontroller. The micro-
controller is set up for SPI master mode with CPHA = 0. To
initiate the operation, the I/O port driving LE is brought low.
Each latch of the
by writing three 8-bit bytes from the microcontroller to the device.
When the third byte is written, bring the LE input high to
complete the transfer.
When power is first applied to the ADF4196, an initialization
sequence is required for the output to become active (see Table 9).
I/O port lines on the microcontroller are also used to detect lock
(MUX
When operating in the SPI master mode, the maximum SPI transfer
rate of the ADuC7023, for example, is 20 Mbps. This means that
the maximum rate at which the output frequency can be changed
is 833 kHz. If using a faster SPI clock, ensure adherence to the
SPI timing requirements that are listed in Table 2.
ADF4196
OUT
configured as lock detect and polled by the port input).
ADuC70xx
family of analog microcontrollers. The ADuC70xx
I/O PORTS
Figure 38.
has a simple SPI-compatible serial interface for
ADF4196
SPICLK
MOSI
ADuC70xx-to-ADF4196
needs a 24-bit word. This is achieved
CLK
DATA
LE
MUX
(LOCK DETECT)
ADF4196
ADF4196
OUT
Interface
and the
Rev. B | Page 27 of 28
Blackfin ADSP-BF527 Interface
Figure 39 shows the interface between the
Blackfin®
ADF4196
easiest way to accomplish this, when using the Blackfin family,
is to use the autobuffered transmit mode of operation with
alternate framing. This provides a means for transmitting an
entire block of serial data before an interrupt is generated.
Set up the word length for eight bits, and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer. Ensure that the clock speeds are
within the maximum limits that are outlined in Table 2.
PCB DESIGN GUIDELINES
The lands on the chip scale package (CP-32-2) are rectangular.
The printed circuit board (PCB) pad for these lands should be
0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. To ensure that the solder joint size
is maximized, center the land on the pad.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as the
exposed pad. To avoid shorting, provide a clearance on the PCB
of at least 0.25 mm between the thermal pad and the inner edges
of the pad pattern.
Thermal vias can be used on the PCB thermal pad to improve the
thermal performance of the package. If vias are used, incorporate
them into the thermal pad at a 1.2 mm pitch grid. Provide a via
diameter between 0.3 mm and 0.33 mm, and plate the via barrel
with 1 oz copper to plug the via. Connect the PCB thermal pad
to A
GND
1 or A
ADSP-BF527
needs a 24-bit serial word for each latch write. The
ADSP-BF527
Figure 39.
GND
I/O FLAGS
2.
SCLK
MOSI
GPIO
ADSP-BF527-to-ADF4196
digital signal processor (DSP). The
CLK
DATA
LE
MUX
(LOCK DETECT)
ADF4196
OUT
ADF4196
Interface
ADF4196
and the