adf4153 Analog Devices, Inc., adf4153 Datasheet - Page 16

• Manufacturer Part Number: adf4153
• Description: Fractional-n Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

ADF4153
When a power-down is activated, the following events occur:
1.
2.
3.
4.
5.
6.
Lock Detect Precision (LDP)
When DB5 is programmed to 0, 24 consecutive PFD cycles of
15 ns must occur before digital lock detect is set. When this bit
is programmed to 1, 40 consecutive reference cycles of 15 ns
must occur before digital lock detect is set.
Phase Detector Polarity
DB6 in the ADF4153 sets the phase detector polarity. When the
VCO characteristics are positive, this should be set to 1. When
they are negative, it should be set to 0.
Charge Pump Current Setting
DB7, DB8, DB9, and DB10 set the charge pump current setting.
This should be set to the charge pump current that the loop
filter is designed with (see Table 9).
REF
Setting DB11 to 0 feeds the REF
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REF
R counter. When the doubler is disabled, the REF
is the active edge at the PFD input to the fractional synthesizer.
When the doubler is enabled, both the rising and falling edges
of REF
When the doubler is enabled and the lowest spur mode is
chosen, the in-band phase noise performance is sensitive to the
REF
as 5 dB for the REF
The phase noise is insensitive to the REF
lowest noise mode and in the lowest noise and spur mode. The
phase noise is insensitive to REF
is disabled.
The maximum allowed REF
enabled is 30 MHz.
NOISE AND SPUR REGISTER, R3
With R3[1, 0] set to [1, 1], the on-chip noise and spur register is
programmed. Table 10 shows the input data format for
programming this register.
IN
IN
All active dc current paths are removed.
The synthesizer counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RF
The input register remains active and capable of loading
and latching data.
Doubler
duty cycle. The phase noise degradation can be as much
IN
IN
become active edges at the PFD input.
frequency by a factor of 2 before feeding into the 4-bit
IN
input is debiased.
IN
duty cycles outside a 45% to 55% range.
IN
frequency when the doubler is
IN
IN
signal directly to the 4-bit RF
duty cycle when the doubler
IN
duty cycle in the
IN
falling edge
Rev. B | Page 16 of 24
Noise and Spur Mode
Noise and spur mode allows the user to optimize a design either
for improved spurious performance or for improved phase
noise performance. When the lowest spur setting is chosen,
dither is enabled. This randomizes the fractional quantization
noise so that it resembles white noise rather than spurious
noise. As a result, the part is optimized for improved spurious
performance. This operation would normally be used when the
PLL closed-loop bandwidth is wide, for fast-locking applica-
tions. (Wide-loop bandwidth is seen as a loop bandwidth
greater than 1/10 of the RF
A wide-loop filter does not attenuate the spurs to the same level
as a narrow-loop bandwidth. When the low noise and spur
setting is enabled, dither is disabled. This optimizes the
synthesizer to operate with improved noise performance.
However, the spurious performance is degraded in this mode
compared to the lowest spur setting.
To further improve noise performance, the lowest noise setting
option can be used, which reduces the phase noise. As well as
disabling the dither, it also ensures that the charge pump is
operating in an optimum region for noise performance. This
setting is extremely useful where a narrow-loop filter band-
width is available. The synthesizer ensures extremely low noise
and the filter attenuates the spurs. The typical performance
characteristics give the user an idea of the trade-off in a typical
WCDMA setup for the different noise and spur settings.
RESERVED BITS
These bits should be set to 0 for normal operation.
OUT
channel step resolution (f
RES
)).