pck953 NXP Semiconductors, pck953 Datasheet - Page 2

• Manufacturer Part Number: pck953
• Description: 50-125 Mhz Pecl Input/9 Cmos Output 3.3 V Pll Clock Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
DESCRIPTION
The PCK953 is a 3.3 V compatible, PLL-based clock driver device
targeted for high performance clock tree designs. With output
frequencies of up to 125 MHz, and output skews of 100 ps, the
PCK953 is ideal for the most demanding clock tree designs. The
devices employ a fully differential PLL design to minimize
cycle-to-cycle and phase jitter.
The PCK953 has a differential LVPECL reference input, along with
an external feedback input. These features make the PCK953 ideal
for use as a zero delay, low skew fanout buffer. The device
performance has been tuned and optimized for zero delay
performance. The MR/OE input pin will reset the internal counters
and 3-State the output buffers when driven HIGH.
The PCK953 is fully 3.3 V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels, while the outputs provide LVCMOS levels with the
ability to drive terminated 50 Ω transmission lines. For series
terminated 50 Ω lines, each of the PCK953 outputs can drive two
traces, giving the device an effective fanout of 1:18. The device is
packaged in a 7 × 7 mm 32-lead LQFP package to provide the
optimum combination of board density and performance.
FEATURES
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2003 Jul 31
Fully integrated PLL
Output frequency up to 125 MHz in PLL mode
Outputs disable in high impedance
LQFP32 packaging
55 ps cycle-to-cycle jitter typical
9 mA quiescent current, I
60 ps static phase offset typical
Less than 10 µA quiescent current, l
20-125 MHz PECL input / 9 CMOS output
3.3 V PLL clock driver
CCA
, typical
CCO
, typical
2
PIN CONFIGURATION
PIN DESCRIPTION
NUMBER
21, 25, 29
11, 1519,
12, 14,
16, 18,
20, 22,
13, 17,
23, 27
24, 26
PIN
3-6
10
28
30
31
32
PECL_CLK
1
2
7
8
9
FB_CLK
V
GNDI
CCA
NC
NC
NC
NC
PECL_CLK
PECL_CLK
VCO_SEL
SYMBOL
BYPASS
FB_CLK
1
2
3
4
5
6
7
8
PLL_EN
MR/OE
Q7-Q0
GNDO
V
GNDI
V
QFB
NC
CCO
CCA
Analog supply voltage. See
Application Information section for
design and layout considerations.
Feedback clock input (CMOS) to
comparator / phase detector
Not connected
Ground pin associated with input
circuitry
LVPECL reference clock input, true
LVPECL reference clock input,
complementary
Master Reset / Output Enable input.
See Function Table
Supply voltage pins associated with
output driver circuitry
Buffered clock outputs (CMOS)
Ground pins associated with output
driver circuitry
Buffered clock output intended to be
fed to feedback pin FB_CLK
PLL Enable input pin. See Function
Table
Bypass input pin. See Function Table
VCO Select input pin. See Function
Table
FUNCTION
PCK953
24
23
22
21
20
19
18
17 GNDO
SW00625
Product data
Q1
V
Q2
GNDO
Q3
V
Q4
CCO
CCO