cy7b9973v Cypress Semiconductor Corporation., cy7b9973v Datasheet - Page 4

• Manufacturer Part Number: cy7b9973v
• Description: High-speed Multi-output Pll Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07430 Rev. *B
Block Diagram Description
(see figure, page 1)
Phase Frequency Detector and Filter
These two blocks accept signals from the reference inputs
(TCLK0, TCLK1 or PECL_CLK) and the FB input (Ext_FB).
Correction information is then generated to control the
frequency of the Voltage Controlled Oscillator (VCO). These
two blocks, along with the VCO, form a (PLL) that tracks the
incoming reference signal.
The Robo973 has a flexible reference input scheme. These
inputs allow the use of either differential LVPECL or one of two
single-ended LVTTL inputs. The reference inputs are tolerant
to hot insertion and can be changed dynamically.
VCO, Control Logic, and Divider
The VCO accepts analog control inputs from the PLL filter
block. The VCO_Sel control pin setting determines the
nominal operational frequency range of the VCO (f
VCO_Sel is HIGH the VCO operating range is 200–480 MHz.
For systems that need lower frequencies, VCO_Sel can be set
LOW, which changes the VCO operating range to
100–240 MHz.
Data Generator
The Data Generator is comprised of four independent banks:
three banks for clock outputs and one bank for feedback. Each
clock output bank has four low-skew, high-fanout output
buffers (Q[a:c][0:3]), controlled by two divide function select
inputs (fsel[a:c][0:1]).
The feedback bank has one high-fanout output buffer (QFB).
This output is usually connected to the selected feedback input
(Ext_FB). This feedback output has three divider function
selects fselFB[0:2].
Inv_Clk Pin Function
The Qc bank has signal invert capability. The four outputs of
the Qc bank will act as two pairs of complementary outputs
when the Inv_Clk pin is driven HIGH. In complementary output
mode, Qc0 and Qc1 are noninverting (i.e., in phase with the
other banks), Qc2 and Qc3 are inverting outputs (i.e., inverted
from the other banks). When the Inv_Clk pin is driven LOW,
the outputs will not invert. Inversion of the outputs are
independent of the divide functions. Therefore, clock outputs
of Qc bank can be inverted and divided at the same time.
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. An unacceptable phase error is declared when the
phase difference between the two inputs is greater than about
700 ps.
NOM
). When
When in the locked state, after four or more consecutive
feedback clock cycles with phase-errors, the LOCK output will
be forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase-errorless
feedback clock cycles are required to allow the LOCK output
to indicate lock condition (LOCK = HIGH).
If the feedback clock is removed after LOCK has gone HIGH,
a Watchdog circuit is implemented to indicate the out-of-lock
condition after a time-out period by deasserting LOCK LOW.
This time-out period is based upon a divided down reference
clock.
This assumes that there is activity on the selected reference
input. If there is no activity on the selected reference input then
the LOCK detect pin may not accurately reflect the state of the
internal PLL.
The LOCK pin has been designed with an intentionally
reduced output drive capability to minimize noise and power
dissipation. This pin will drive logic, but not Thevenin-termi-
nated transmission lines. It is also unaffected by the MR/OE
input and is always active.
PLL Bypass Mode Description
The device will enter PLL bypass mode when the PLL_En is
driven LOW. In factory PLL bypass mode, the device will
operate with its internal PLL disconnected; input signals
supplied to the reference input will be used in place of the PLL
output. In PLL bypass mode the Ext_FB input is ignored. All
functions of the device are still operational in PLL bypass
mode.
Factory Test Reset
When in PLL bypass mode (PLL_En = LOW), the device can
be reset to a deterministic state by driving the MR/OE input
LOW. When the MR/OE input is driven LOW in PLL bypass
mode, all clock outputs will go to HI-Z; after the selected
reference clock pin has 5 positive transitions, all the internal
finite state machines (FSM) will be set to a deterministic state.
The deterministic state of the state machines will depend on
the configurations of the divide selects and frequency select
input. All clock outputs will stay in high-impedance mode and
all FSMs will stay in the deterministic state until MR/OE is
deasserted. When MR/OE is deasserted (with PLL_En still at
LOW), the device will reenter PLL bypass mode.
Safe Operating Zone
The device will operate below its maximum allowable junction
temperature (t
divide with all outputs loaded to the data sheet maximum (i.e.,
with 25-pF load and 0-m/s air flow).
J
< 150°C) in any configuration of multiply or
RoboClock
CY7B9973V
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