cy7b9973v Cypress Semiconductor Corporation., cy7b9973v Datasheet

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cy7b9973v

Manufacturer Part Number
cy7b9973v
Description
High-speed Multi-output Pll Clock Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07430 Rev. *B
Features
• 10-MHz – 200-MHz output operation
• Output-to-output skews < 350 ps
• 13 LVTTL 50% duty-cycle outputs capable of driving
• Phase-locked loop (PLL) LOCK indicator
• 3.3V LVTTL/LV differential (LVPECL) hot insertable
• Multiply/divide ratios of (4, 6, 8, 10, 12, 16, 20):(2, 4, 6,
• Operation with outputs operating at up to 10x input
• Low cycle-to-cycle jitter (< ±75 ps peak-peak)
• Single 3.3V ± 10% supply
• Pin-compatible with Motorola MPC973
• 52-pin TQFP package
Logic Diagram
50Ω terminated lines
reference inputs
8, 10, 12, 16, 20)
frequency
fselFB0:1 (27,26)
PECL_CLK (11)
PECL_CLK (12)
fsela0:1 (43,42)
fselb0:1 (41,40)
fselc0:1 (20,19)
VCO_Sel (52)
TCLK_Sel (8)
Ext_FB (31)
Inv_Clk (14)
TCLK1 (10)
PLL_En (6)
Ref_Sel (7)
fselFB2 (5)
MR/OE (2)
TCLK0 (9)
0
1
High-Speed Multi-Output PLL Clock Buffer
1
0
3901 North First Street
DETECTOR
PHASE
2
2
2
2
Reset
Functional Description
The CY7B9973V Low-Voltage PLL Clock Buffer offers
user-selectable frequency control over system clock functions.
This twelve output clock driver provides the system integrator
selectable frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:3, 5:1, 5:2,
5:3, 6:1 and 6:5 between outputs. An additional output is
dedicated to providing feedback information to allow the
internal PLL to multiply an external reference frequency by 4,
6, 8, 10, 12, 16 or 20. The completely integrated PLL reduces
jitter and simplifies board layout.
The thirteen configurable outputs can each drive terminated
transmission lines with impedances as low as 50Ω while deliv-
ering minimal and specified output skews at LVTTL levels.
The CY7B9973V has a flexible reference input scheme with
three different hot-insertion capable inputs. These inputs allow
the use of either differential LVPECL or single-ended LVTTL
inputs which can be dynamically selected to provide the
reference frequency.
Data Generator
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
LPF
÷4, ÷6, ÷8, ÷10
VCO
0
1
San Jose
÷2/÷1
÷2
,
0
1
CA 95134
Revised September 27, 2006
D Q
D Q
D Q
D Q
D Q
RoboClock
CY7B9973V
408-943-2600
Qb3 (32)
LOCK (25)
Qa0 (50)
Qa2 (46)
Qa3 (44)
Qb0 (38)
Qb1 (36)
Qb2 (34)
Qc0 (23)
Qc1 (21)
Qc2 (18)
Qc3 (16)
QFB (29)
Qa1 (48)
®
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cy7b9973v Summary of contents

Page 1

... The thirteen configurable outputs can each drive terminated transmission lines with impedances as low as 50Ω while deliv- ering minimal and specified output skews at LVTTL levels. The CY7B9973V has a flexible reference input scheme with three different hot-insertion capable inputs. These inputs allow the use of either differential LVPECL or single-ended LVTTL inputs which can be dynamically selected to provide the reference frequency ...

Page 2

... VCO/2 ÷ 6 Ref_Sel Controlled by TCLK_Sel ÷ 8 TCLK_Sel TCLK0 ÷ 10 PLL_En Bypass PLL ÷ 8 MR/OE Master Reset/Output Hi-Z Enable Outputs ÷ 12 Inv_Clk Noninverted Qc2, Qc3 ÷ 16 ÷ 20 ® RoboClock CY7B9973V 27 26 fselFB1 25 LOCK 24 GNDO 23 Qc0 22 VCCO 21 Qc1 20 fselc0 19 fselc1 18 Qc2 17 VCCO 16 Qc3 15 GNDO 14 Inv_Clk ...

Page 3

... It is always active and does not high impedance state. This output provides TEST MODE information when PLL_En is LOW. Note: 1. Includes internal PULL-UP. If this pin is left unconnected it will assume a HIGH level. Document #: 38-07430 Rev. *B RoboClock CY7B9973V Description Page ® [+] Feedback ...

Page 4

... LOW), the device will reenter PLL bypass mode. Safe Operating Zone The device will operate below its maximum allowable junction temperature (t < 150°C) in any configuration of multiply or J divide with all outputs loaded to the data sheet maximum (i.e., with 25-pF load and 0-m/s air flow). ® RoboClock CY7B9973V Page [+] Feedback ...

Page 5

... CMR 3. The CY7B9973V clock outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge. 4. Inputs have pull-up resistors which affect input current. 5. Tested initially and after any design or process changes that may affect these parameters. ...

Page 6

... L (a) LVTTL AC Test Load 2.0V 2.0V 10% 0.8V 1.0V < < (c) LVPECL Input Test Waveform does not include jitter. PD for GND for t ). For t and t CC OZL OZH OZL OZH RoboClock CY7B9973V Min. Typ. Max. Unit 0.15 – 1.2 ns. 0.15 – 1.2 ns CYCLE CYCLE CYCLE – ...

Page 7

... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges refdc refdc jitter Package Type A52 52-Lead Thin Quad Flat Pack ® RoboClock CY7B9973V Operating Range Commercial 51-85131-** Page [+] Feedback ...

Page 8

... Document History Page Document Title: CY7B9973V RoboClock Document Number: 38-07430 REV. ECN No. Issue Date ** 115842 06/10/02 *A 128182 09/15/03 *B 506217 See ECN Document #: 38-07430 Rev. *B ® High-Speed Multi-Output PLL Clock Buffer Orig. of Change Description of Change HWT New Data Sheet Added phase and period jitter specifications ...

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