cy7b9950 Cypress Semiconductor Corporation., cy7b9950 Datasheet - Page 3

• Manufacturer Part Number: cy7b9950
• Description: 2.5/3.3v, 200 Mhz High-speed Multi-phase Pll Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Table 1. Pin Definitions
Device Configuration
The outputs of the CY7B9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 2
Table 2. Output Divider Settings — Bank 3
Document #: 38-07338 Rev. *D
29
13
27
22
4
24, 23, 26,
25, 1, 32, 3,
2
31
19, 20, 15,
16, 10, 11, 6,
7
21
12
5
14,30
8,9,17,18,28
Notes
1. “PD” indicates an internal pull-down and “PU” indicates an internal pull-up. “3” indicates a three-level input buffer
2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
4. These states are used to program the phase of the respective banks (see
high-frequency filtering characteristic are cancelled by the lead inductance of the traces.
remain in effect unless nF[1:0] = LL.
Pin
Other
3F[1:0]
and
HH
LL
Table
[4]
V
V
V
nQ[1:0]
PE/HD
nF[1:0]
Name
V
TEST
sOE#
DDQ1
DDQ3
DDQ4
REF
V
FB
FS
DD
SS
3, respectively.
[2]
[2]
[2]
[2]
PWR
PWR
PWR
PWR
PWR
I, PD
I, PU
IO
O
K — Bank3 Output Divider
I
I
I
I
I
[1]
LVTTL/LVCMOS Reference Clock Input.
Three-level
Three-level
Three-level
Three-level
Two-level
LVTTL
LVTTL
Power
Power
Power
Power
Power
Type
2
4
1
Feedback Input.
When MID or HIGH, disables Phase-locked Loop (PLL)
outputs of Bank 1 and Bank 2. REF also goes to outputs of Bank 3 and Bank
4 through output dividers K and M. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0
and 2Q1) in a LOW state (for PE = H or M) – 2Q0, and 2Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level
and sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual
banks when nF[1:0] = LL. Set sOE# LOW for normal operation.
Selects Positive or Negative Edge Control and High or Low Output Drive
Strength. When LOW/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock, respectively. When at MID level,
the output drive strength is increased and the outputs synchronize with the
positive edge of the reference clock (see
Select Frequency and Phase of the Outputs (see
on page 4,
Selects VCO Operating Frequency Range (see
Four Banks of Two Outputs (see
Power Supply for Bank 1 and Bank 2 Output Buffers (see
4 for supply level constraints).
Power Supply for Bank 3 Output Buffers (see
level constraints).
Power Supply for Bank 4 Output Buffers (see
level constraints).
Power Supply for Internal Circuitry (see
constraints).
Ground
Table 5
Table 6
on page 4).
Table 3. Output Divider Settings — Bank 4
The three-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B9950 PLL operating frequency range that cor-
responds to each FS level is given in
on page 4, and
Other
4F[1:0]
LL
[4]
Description
Table 6
Table
2,
Table 7
on page 4).
Table 8
Table
M — Bank4 Output Divider
Table 8
Table 8
on page 4).
3, and
Table 5
on page 4 for supply level
Table
Table 4
on page 4 for supply
on page 4 for supply
Table 4
on page 4)
2,
[3]
2
1
. REF goes to
Table
Table 8
on page 4.
CY7B9950
on page 4)
3,
on page
Table 4
Page 3 of 12
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