cy7b9950 Cypress Semiconductor Corporation., cy7b9950 Datasheet
cy7b9950
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cy7b9950 Summary of contents
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... Document #: 38-07338 Rev. *D 2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer Description The CY7B9950 RoboClock eight-output, 200 MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high performance computer and communication systems. The user can program the phase of the output banks through nF[0:1] pins ...
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... Pinouts Figure 1. Pin Diagram - 32 Pin TQFP package Top view Document #: 38-07338 Rev. *D 3F1 1 24 1F1 2 4F0 23 1F0 3 4F1 22 sOE# 4 PE/HD 21 VDDQ1 CY7B9950 5 VDDQ4 20 1Q0 6 4Q1 19 1Q1 7 4Q0 18 VSS 8 VSS VSS 17 CY7B9950 Page [+] Feedback [+] Feedback ...
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... PWR Power DD 8,9,17,18,28 V PWR Power SS Device Configuration The outputs of the CY7B9950 can be configured to run at frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 2 and Table 3, respectively. Table 2. Output Divider Settings — Bank 3 3F[1:0] K — Bank3 Output Divider ...
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... PE/HD pin controls the output buffer drive strength as indicated in Table 7. The CY7B9950 features split power supply buses for Banks 1 and 2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V and 2.5V output signals from one device. The core power supply (VDD) must be set a level that is equal or higher than on any one of the output power supplies ...
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... V = max., (sOE (PE/HD = L/H), (nQ[0:1 (PE/HD = MID), (nQ[0:1 –12 mA (PE/HD = L/H), (nQ[0:1 –20 mA (PE/HD = MID), (nQ[0:1 max., TEST = MID, REF = LOW, DD sOE# = LOW, outputs not loaded At 100 MHz CY7B9950 Min Max Unit 2.375 2.625 V 2.97 3. – 0.3 – – 0 –65 +150 ° ...
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... max., (sOE (PE/HD = L/H), (nQ[0:1 (PE/HD = MID), (nQ[0:1 –12 mA (PE/HD = L/H), (nQ[0:1 –24 mA (PE/HD = MID), (nQ[0:1 max., TEST = MID, REF = LOW, DD sOE# = LOW, outputs not loaded At 100 MHz CY7B9950 Min Max Unit 2.97 3.63 V – 0.8 V 2.0 – – 0.6 – – 0 ...
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... For All Other Outputs Figure 3. Output Waveforms t OFALL 1.7V VTH =1.25V 0.7V Figure 4. Test Waveforms ≤ VTH =1.25V Condition 0.8V – 2.0V HIGH or LOW FS = LOW FS = MID FS = HIGH CY7B9950 150Ω 150Ω ORISE OFALL t PWH t PWL 2.5V LVTTL OUTPUT WAVEFORM ≤ ≤ ...
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... Document #: 38-07338 Rev. *D Condition . U ,V ,temp, air DDQ 3.3V and at 1.7V for 3.3V and at 0.7V for 3.3V and 0.7V–1. 2.5V 2.5V with REF rise/fall times of 0.5 ns between 0.8V – 2.0V. DD CY7B9950 Min Typ Max Unit 6 – 200 MHz 200 – 400 MHz 0.25 – 3.5 MHz – 50 100 ps – ...
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... OTHER Q INVERTED Q REF DIVIDED BY 2 REF DIVIDED BY 4 Document #: 38-07338 Rev. *D Figure 5. Timing Definitions t REF 0DCV 0DCV t t SKEW PR SKEW PR t SKEW 0,1 t SKEW 0 SKEW 1 SKEW 1 t SKEW3 t SKEW 3 t SKEW1,3,4 CY7B9950 t CCJ1-12 t SKEW3 t SKEW 1,3,4 Page [+] Feedback [+] Feedback ...
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... TQFP – Tape and Reel CY7B9950AI 32 TQFP CY7B9950AIT 32 TQFP – Tape and Reel Pb-free CY7B9950AXC 32 TQFP CY7B9950V-5AXC 32 TQFP CY7B9950AXCT 32 TQFP – Tape and Reel CY7B9950AXI 32 TQFP CY7B9950AXIT 32 TQFP – Tape and Reel Document #: 38-07338 Rev. *D Product Flow Commercial, 0° to 70°C Not for new design Commercial, 0° ...
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... Package Drawing and Dimension Figure 6. 32-lead Thin Plastic Quad Flatpack 1.0 mm A32 Document #: 38-07338 Rev. *D CY7B9950 51-85063-*B Page [+] Feedback [+] Feedback ...
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... Document History Page ® Document Title: RoboClock CY7B9950 2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer Document Number: 38-07338 Rev. ECN No. Issue Date Change ** 121663 11/25/02 *A 122548 12/12/02 *B 124646 03/05/03 *C 433662 See ECN *D 1562063 See ECN PYG/AESA Added Lead-free CY7B9940V-5AXC to Ordering Information © Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...