cy7b9940v Cypress Semiconductor Corporation., cy7b9940v Datasheet - Page 4

• Manufacturer Part Number: cy7b9940v
• Description: High Speed Multifrequency Pll Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Pin Definitions
Note
Document Number: 38-07271 Rev. *C
FBKA
REFA+, REFA–
REFB+, REFB–
REFSEL
FS
FBDS[0:1]
DIS[1:2]
LOCK
Output_Mode
QFA[0:1]
[1:2]Q[A:B][0:1]
VCCN
VCCQ
GND
3. For all tri-state inputs, HIGH indicates a connection to V
[3]
holds an unconnected input to V
Name
[3]
[3]
Input
Input
Input
Input
Input
Input
Output
Input
Output
Output
I/O
CC
LVTTL
LVTTL/
LVDIFF
LVTTL
3 Level
Input
3 Level
Input
LVTTL
LVTTL
3 Level
Input
LVTTL
LVTTL
PWR
PWR
PWR
/2.
Type
VCCN
VCCN
2QA1
2QB1
2QB0
2QA0
GND
GND
GND
GND
GND
Feedback Input.
Reference Inputs: These inputs operate as either differential PECL or single ended TTL
reference inputs to the PLL. When operating as a single ended LVTTL input, leave the
complementary input must be left open.
Reference Select Input: The REFSEL input controls reference input configuration. When
LOW, it uses the REFA pair as the reference input. When HIGH, it uses the REFB pair as
the reference input. This input has an internal pull down.
Frequency Select: Set this input according to the nominal frequency (f
Feedback Divider Function Select. These inputs determine the function of the QFA0 and
QFA1 outputs. See
Output Disable: Each input controls the state of the respective output bank. When HIGH,
the output bank is disabled to the “HOLD OFF” or “HI-Z” state; the disable state is deter-
mined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled. See
These inputs each have an internal pull down.
PLL Lock Indicator: When HIGH, this output indicates that the internal PLL is locked to
the reference signal. When LOW, the PLL is attempting to acquire lock.
Output Mode: This pin determines the clock outputs’ disable state. When this input is HIGH,
the clock outputs disable to high impedance (HI-Z). When this input is LOW, the clock
outputs disables to “HOLD OFF” mode. When in MID, the device enters factory test mode.
Clock Feedback Output: This pair of clock outputs connects to the FB input. These outputs
have numerous divide options. The function is determined by the setting of the FBDS[0:1]
pins.
Clock Output.
Output Buffer Power: Power supply for each output pair.
Internal Power: Power supply for the internal circuitry.
Device Ground.
CC
, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
1
2
3
4
5
6
7
8
9
10
11
44
12
43
13
CY7B9930V/40V
42
14
44-Pin TQFP
41
15
Table
40
16
39
17
38
2.
18
37
19
36 35 34
20 21 22
33
32
31
30
29
28
27
26
25
24
23
Description
VCCQ
REFA+
REFA –
REFSEL
REFB–
REFB+
FS
GND
VCCQ
DIS2
DIS1
CY7B9930V, CY7B9940V
RoboClockII™ Junior,
NOM
). See
Table
Page 4 of 11
Table
3.
1.
[+] Feedback
[+] Feedback