cy7b9940v Cypress Semiconductor Corporation., cy7b9940v Datasheet - Page 2

• Manufacturer Part Number: cy7b9940v
• Description: High Speed Multifrequency Pll Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+ or REFB–) and the FB input (FBKA). Correction
information is then generated to control the frequency of the
Voltage Controlled Oscillator (VCO). These two blocks, along
with the VCO, form a Phase-Locked Loop (PLL) that tracks the
incoming REF signal.
The RoboClockII™ Junior has a flexible REF input scheme.
These inputs allow the use of either differential LVPECL or single
ended LVTTL inputs. To configure as single ended LVTTL inputs,
leave the complementary pin to 1.5V), then use the other input
pin as an LVTTL input. The REF inputs are also tolerant to hot
insertion.
The REF inputs can be changed dynamically. When changing
from one reference input to the other reference input of the same
frequency, the PLL is optimized to ensure that the clock outputs
period is not less than the calculated system budget (t
(nominal reference clock period) – t
t
VCO, Control Logic, and Divide Generator
The VCO accepts analog control inputs from the PLL filter block.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (f
f
versions of the RoboClockII Junior, a low speed device
(CY7B9930V) where f
a high speed device (CY7B9940V), which ranges from 24 MHz
to 200 MHz. The FS setting for each device is shown in
The f
Table 1. Frequency Range Select
Document Number: 38-07271 Rev. *C
Notes
LOW
MID
HIGH
PDEV
NOM
1. The level to be set on FS is determined by the “nominal” operating frequency (f
2. The maximum output frequency is 200 MHz.
FS
the undivided mode. The REF and FB are at f
NOM
[1]
is directly related to the VCO frequency. There are two
(max. period deviation)) while reacquiring lock.
frequency is seen on “divide-by-one” outputs.
Min.
12
24
48
CY7B9930V
f
NOM
NOM
(MHz)
ranges from 12 MHz to 100 MHz, and
Max.
100
26
52
CCJ
NOM
Min.
(cycle-to-cycle jitter) –
24
48
96
when the output connected to FB is undivided.
CY7B9940V
f
NOM
NOM
) of the device.
(MHz)
MIN
200
Max.
100
52
Table
= t
[2]
REF
1.
NOM
Divide Matrix
The Divide Matrix is comprised of three independent banks: two
banks of clock outputs and one bank for feedback. Each clock
output bank has two pairs of low-skew, high fanout output buffers
([1:2]Q[A:B][0:1]), and an output disable (DIS[1:2]).
The feedback bank has one pair of low-skew, high fanout output
buffers (QFA[0:1]). One of these outputs may connect to the
selected feedback input (FBKA+). This feedback bank also has
two divider function selects FBDS[0:1].
The divide capabilities for each bank are shown in
Table 2. Output Divider Function
Output Disable Description
The outputs of Bank 1 and Bank 2 can be independently put into
a HOLD OFF or high impedance state. The combination of the
Output_Mode and DIS[1:2] inputs determines the clock outputs’
state for each bank. When the DIS[1:2] is LOW, the outputs of
the corresponding bank are enabled. When the DIS[1:2] is HIGH,
the outputs for that bank are disabled to a high impedance (HI-Z)
or HOLD OFF state depending on the Output_Mode input.
Table 3
) of the V
FBDS1
HIGH
HIGH
HIGH
LOW
LOW
LOW
MID
MID
MID
CO
defines the disabled output functions.
Function
. f
Selects
NOM
always appears on an output when the output is operating in
FBDS0
HIGH
HIGH
HIGH
LOW
LOW
LOW
MID
MID
MID
CY7B9930V, CY7B9940V
RoboClockII™ Junior,
Bank 1
Output Divider Function
/1
/1
/1
/1
/1
/1
/1
/1
/1
Bank 2
/1
/1
/1
/1
/1
/1
/1
/1
/1
Table
Page 2 of 11
Feedback
Bank
/10
/12
/1
/2
/3
/4
/5
/6
/8
2.
[+] Feedback
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