cy7b9911-7jc Cypress Semiconductor Corporation., cy7b9911-7jc Datasheet - Page 10

• Manufacturer Part Number: cy7b9911-7jc
• Description: Programmable Skew Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

range of delays, if the output connected to FB is also skewed. As
“Zero Skew”, +tU, and –tU are defined relative to output groups
and the PLL aligns the rising edges of REF and FB, wider output
skews are created by proper selection of the xFn inputs. For
example, a +10 tU between REF and 3Qx is achieved by
connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID,
and 3F1 = High. (Since FB aligns at –4 tU and 3Qx skews to +6
tU, a total of +10 tU skew is realized.) Many other configurations
are realized by skewing both the output used as the FB input and
skewing the other outputs.
Figure 4
In this example the 4Q0 output used as the FB input is
programmed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew. When 4F0 and
4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising edge of the FB input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs
to become the “inverted” outputs with respect to the REF input.
By selecting the output to connect to FB, you can have two
inverted and six non-inverted outputs or six inverted and two
non-inverted outputs. The correct configuration is determined by
the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q
outputs is also skewed to compensate for varying trace delays
independent of inversion on 4Q.
Document Number: 38-07209 Rev. *B
shows an example of the invert function of the PSCB.
Figure 5. Inverted Output Connections
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
Figure 5
The 3Q0 output is programmed to divide by four and is sent back
to FB. This causes the PLL to increase its frequency until the 3Q0
and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx
outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two, that results in a 40 MHz waveform
at these outputs. Note that the 20 and 40 MHz clocks fall simul-
taneously and are out of phase on their rising edge. This enables
the designer to use the rising edges of the 1⁄2 frequency and 1⁄4
frequency outputs without concern for rising edge skew. The
2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed
by programming their select inputs accordingly. Note that the FS
pin is wired for 80 MHz operation because that is the frequency
of the fastest output.
Figure 6
2Q0 is fed back to the FB input and programmed for zero skew.
3Qx is programmed to divide by four. 4Qx is programmed to
divide by two. Note that the falling edges of the 4Qx and 3Qx
outputs are aligned. This enables use of the rising edges of the
1⁄2 frequency and 1⁄4 frequency without concern for skew
mismatch. The 1Qx outputs are programmed to zero skew and
are aligned with the 2Qx outputs. In this example, the FS input
is grounded to configure the device in the 15 to 30 MHz range
since the highest frequency output is running at 20 MHz.
20 MHz
20 MHz
Figure 6. Frequency Multiplier with Skew Connections
Figure 7. Frequency Divider Connections
demonstrates the PSCB in a clock divider application.
illustrates the PSCB configured as a clock multiplier.
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
REF
RoboClock+™
40 MHz
20 MHz
80 MHz
CY7B9911
10 MHz
20 MHz
5 MHz
Page 10 of 13
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