cy7b9911-7jc Cypress Semiconductor Corporation., cy7b9911-7jc Datasheet

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cy7b9911-7jc

Manufacturer Part Number
cy7b9911-7jc
Description
Programmable Skew Clock Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Features
Cypress Semiconductor Corporation
Document Number: 38-07209 Rev. *B
Logic Block Diagram
All output pair skew <100 ps typical (250 max)
3.75 to 100 MHz output operation
User selectable output functions
Zero input to output delay
50% duty cycle outputs
Outputs drive 50Ω terminated lines
Low operating current
32-pin PLCC/LCC package
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Selectable skew to 18 ns
Inverted and non-inverted
Operation at ½ and ¼ input frequency
Operation at 2x and 4x input frequency (input as low as 3.75
MHz)
REF
FB
TEST
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
FS
PHASE
FREQ
DET
SELECT
(THREE
INPUTS
LEVEL)
198 Champion Court
FILTER
Programmable Skew Clock Buffer
GENERATOR
TIME UNIT
VCO AND
SELECT
MATRIX
Functional Description
The CY7B9911 High Speed Programmable Skew Clock Buffer
(PSCB) offers user selectable control over system clock
functions. This multiple output clock driver provides the system
integrator with functions necessary to optimize the timing of high
performance computer systems. Each of the eight individual TTL
drivers, arranged in four pairs of user controllable outputs, can
drive terminated transmission lines with impedances as low as
50Ω. They deliver minimal and specified output skews and full
swing logic levels.
Each output is hardwired to one of nine delay or function config-
urations. Delay increments of 0.6 to 1.5 ns are determined by the
operating frequency with outputs able to skew up to ±6 time units
from their nominal “zero” skew position. The completely
integrated PLL allows cancellation of external load and trans-
mission line delay effects. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions,
you can create output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that is multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty enabling maximum system clock speed and
flexibility.
SKEW
San Jose
,
CA 95134-1709
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
RoboClock+™
Revised June 20, 2007
CY7B9911
408-943-2600
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cy7b9911-7jc Summary of contents

Page 1

... Document Number: 38-07209 Rev. *B Programmable Skew Clock Buffer Functional Description The CY7B9911 High Speed Programmable Skew Clock Buffer (PSCB) offers user selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer systems ...

Page 2

... CCQ CY7B9911 CCN 4Q1 10 24 4Q0 23 11 GND 12 22 GND Description Table 1. Table 2. Table 2. Table 2. Table 2. CY7B9911 RoboClock+™ 2F0 GND 1F1 1F0 V CCN 1Q0 1Q1 GND GND Table 2. Table 2 Table 2 Table 2 Page [+] Feedback ...

Page 3

... Calculation U MID MID MID HIGH Approximate HIGH LOW Which HIGH MID 22.7 HIGH HIGH 38.5 62.5 CY7B9911 RoboClock+™ selected. U [1] Output Functions 1Q0, 1Q1, 3Q0, 3Q1 4Q0, 4Q1 3F0, 4F0 2Q0, 2Q1 –4t Divide by 2 Divide –3t –6t – –2t – ...

Page 4

... The TEST input is a three level input. In normal system operation, this pin is connected to ground, enabling the CY7B9911 to operate as explained in the previous section (for testing purposes). Any of the three level inputs can have a removable jumper to ground or be tied LOW through a 100Ω ...

Page 5

... CY7B9911 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 7. Total output current per output pair is approximated by the following expression that includes device current plus load current: CY7B9911:ICCN = [(4 + 0.11F) + [((835 – ...

Page 6

... Parameter Description C Input Capacitance IN AC Test Loads and Waveforms 5V R1=130 R1 R2= (Includes fixture and probe capacitance TTL AC Test Load (CY7B9911) Document Number: 38-07209 Rev. *B Test Conditions ° MHz 5. 2.0V V =1.5V th 0.8V 0.0V ≤1ns TTL Input Test Waveform (CY7B9911) CY7B9911 RoboClock+™ ...

Page 7

... AC Test Loads and Waveforms . Other outputs are divided or inverted but not shifted. U delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by within specified limits. PD CY7B9911 RoboClock+™ CY7B9911–7 Max Min Typ Max ...

Page 8

... INVERTED Q REF DIVIDED BY 2 REF DIVIDED BY 4 Document Number: 38-07209 Rev. *B Figure 2. AC Timing Diagrams t t REF RPWL t RPWH t ODCV t ODCV t t SKEWPR, SKEWPR SKEW0,1 SKEW0,1 t SKEW2 t SKEW3,4 t SKEW3,4 t SKEW1,3, 4 CY7B9911 RoboClock+™ SKEW2 t SKEW3,4 t SKEW2,4 Page [+] Feedback ...

Page 9

... FB and REF inputs and aligns their rising edges to make certain that all outputs have precise phase alignment. Clock skews is advanced by ±6 time units (tU) when using an output selected for zero skew as the feedback. There is a wider CY7B9911 RoboClock+™ LOAD Z ...

Page 10

... The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the MHz range since the highest frequency output is running at 20 MHz. CY7B9911 40 MHz 20 MHz 80 MHz 10 MHz ...

Page 11

... MHz 2Q0 ZEROSKEW 2Q1 1Q0 1Q1 80 MHz SKEWED4ns REF L1 L2 4Q0 4Q1 3Q0 3Q1 L3 2Q0 2Q1 1Q0 L4 1Q1 CY7B9911 RoboClock+™ LOAD MHz LOAD 20 MHz Z 0 LOAD Z 0 LOAD Z 0 LOAD Z 0 LOAD Z 0 LOAD ...

Page 12

... Figure 8 shows the CY7B9911 connected in series to construct a zero-skew clock distribution tree between boards. Delays of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay) necessary to connect them to the master clock source, Ordering Information ...

Page 13

... Document History Page Document Title: CY7B9911 RoboClock+™ Programmable Skew Clock Buffer Document Number: 38-07209 Orig. of REV. ECN NO. Issue Date Change ** 110342 12/21/01 *A 1199925 See ECN KVM/AESA Added Tape and Reel part in Ordering Information *B 1286064 See ECN © Cypress Semiconductor Corporation, 2001-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...

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