w83194r-81 Winbond Electronics Corp America, w83194r-81 Datasheet - Page 16

• Manufacturer Part Number: w83194r-81
• Description: 100mhz Clock Chipset
• Manufacturer: Winbond Electronics Corp America

10.0 POWER MANAGEMENT TIMING
For synchronous Chipset, CPU_STOP# pin is a synchronous “a ctive low ”i nput pin used to stop the
CPU clocks for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU
locks off latency is less then 2 CPU clocks.
10.2 PCI_STOP# Timing Diagram
For synchronous Chipset, PCI_STOP# pin is a synchronous
PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output
with full pulse width. In this case, PCI
latency is less then 1 PCI clocks.
10.1 CPU_STOP# Timing Diagram
PCI_STOP#
PCICLK[0:4]
PCICLK_F
CPUCLK
(Internal)
(Internal)
CPUCLK[0:3]
PCICLK
CPU_STOP#
PCICLK_F
CPUCLK
(Internal)
(Internal)
PCICLK
SDRAM
1
1
2
locks on latency “ is less than 1 PCI clocks and locks off
2
- 16 -
locks on latency “ is less than 2 CPU clocks and
1
ctive low ” input pin used to stop the
1
Publication Release Date: Dec. 1998
2
2
W83194R-81
PRELIMINARY
Revision 0.20