w83194br-655 Winbond Electronics Corp America, w83194br-655 Datasheet - Page 16

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w83194br-655

Manufacturer Part Number
w83194br-655
Description
Clock For Sis Chipsets Winbond Clock Generator
Manufacturer
Winbond Electronics Corp America
Datasheet
7.11 Register 10:N & N3 (Default: 3Bh)
7.12 Register 11: Spread Spectrum Programming (Default: 0Eh)
7.13 Register 12: Divisor and Step-less Enable Control (Default: 89h)
BIT
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
NVAL<9>
N3VAL<6>
N3VAL<5>
N3VAL<4>
N3VAL<3>
N3VAL<2>
N3VAL<1>
N3VAL<0>
SP_UP [3]
SP_UP [2]
SP_UP [1]
SP_UP [0]
SP_DOWN [3]
SP_DOWN [2]
SP_DOWN [1]
SP_DOWN [0]
M_NACC_EN
KVAL<9>
KVAL<5>
Reserved
Reserved
KVAL<2>
KVAL<1>
KVAL<0>
NAME
NAME
NAME
PWD
PWD
X
X
X
X
X
X
X
1
0
0
0
0
1
1
1
0
PWD
X
X
X
X
X
X
X
X
Enable variable accumulation period for M divisor
1: Enable, 0: Disable (Original timing)
Define the ZCLK divider ratio
Table-2 integrate the all divider configuration
Reserved
Define the CPU divider ratio
Refer to Table-2
Spread Spectrum Up Counter bit 3 ~ bit 0.
Spread Spectrum Down Counter bit 3 ~ bit 0
2’s complement representation.
Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000
Programmable N divisor bit 9.
Programmable N3 divisor bit 6 ~0 for programmable
SRC clock.
PS:
Frequency range: 86.8M ~ 115.2M
Resolution: 224K
W83194BR-655/W83194BG-655
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DESCRIPTION
DESCRIPTION
DESCRIPTION

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