w83194br-730 Winbond Electronics Corp America, w83194br-730 Datasheet

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w83194br-730

Manufacturer Part Number
w83194br-730
Description
166mhz Clock For Sis Chipset
Manufacturer
Winbond Electronics Corp America
Datasheet
1.0 GENERAL DESCRIPTION
The W83194BR-730 is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as AMD K7. W83194BR-730 provides 64 CPU/PCI frequencies which are
selectable with smooth transitions by hardware or software. W83194BR-730 also provides 13 SDRAM
clocks.
The W83194BR-730 provides step-less frequency programming by controlling the VCO freq. and the
programmable PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the
RESET# pin will output 4ms pulse signal.
The W83194BR-730 accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at
0~-0.5% or ±0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency
selection through I
CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots(ISA, PCI,
CPU, DIMM) is not recommend.
2.0 PRODUCT FEATURES
Supports AMD CPU with I
3 CPU clocks (one free-running CPU clock)
13 SDRAM clocks for 3 DIMMs
6 PCI synchronous clocks
2 AGP clocks
2 REF clocks as 14.318MHz outputs
< 250ps skew among CPU and SDRAM clocks
< 250ps skew among PCI clocks
MODE pin for power Management and RESET# out when system hang
One 48 MHz for USB & one 24_48 MHz for super I/O
48-pin SSOP package
Skew from CPU(earlier) to PCI clock 1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 66 MHz to 200 MHz CPU
Stepless frequency programming by controlling the VCO freq. and the clock output divisor ratio
Programmable skew for CPU to SDRAM and CPU to AGP clock outputs
I
±0.25% or 0~-0.5% spread spectrum function to reduce EMI
Programmable registers to enable/stop each output and select modes
2
C 2-Wire serial interface and I
2
C interface. The device meets the Pentium power-up stabilization, which requires
2
C.
2
C read back
- 1 -
166MHZ CLOCK FOR SIS CHIPSET
Publication Release Date: Oct. 2000
W83194BR-730
Revision 0.60

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w83194br-730 Summary of contents

Page 1

... PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. The W83194BR-730 accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at 0~-0.5% or ±0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency ...

Page 2

... SDRAM Vss 18 31 SDRAM 8/PD SDRAM 9/SDRAM_STOP# 20 VssSD 29 21 SDRAM 10/PCI_STOP SDRAM11/CPU_STOP SDRAM12 24 25 VddSD I/O FUNCTION IN Crystal input with internal loading capacitors and feedback resistors. OUT Crystal output at 14.318MHz nominally. Publication Release Date:Oct. 2000 - 2 - W83194BR-730 PRELIMINARY Revision 0.60 ...

Page 3

... PCICLK [2:4]^ 10,11,12 PCICLK5/ 13 RESET$ AGPCLK0/ 16 SEL24#_48* AGPCLK1/ 17 Mode1* W83194BR-730 I/O FUNCTION OD Open drain output clock for host frequencies CPU. Powered by VddLCPU. Stopped if CPU_STOP# is low. OD Open drain clock for chipset. Stopped if CPU_STOP# is low and Register1 bit7=0. The same phase as CPUC0$. OUT SDRAM clock outputs. The same phase as CPUC0$ OUT Pin21 & ...

Page 4

... Power supply for CPUC0,T0,CS_C1, either 2.5V or 3.3V. 7 Power supply for PCICLK[0:5], 3.3V. Power supply for SDRAM[0:12], and CPU PLL core, nominal 3.3V. 19 Power for 24 & 48MHz output buffers and fixed PLL core. Circuit Ground W83194BR-730 PRELIMINARY FUNCTION FUNCTION FUNCTION Publication Release Date:Oct. 2000 Revision 0.60 ...

Page 5

... After that, the sequence described below (Register 0, Register 1, 8 bits dummy Ack Byte count Byte 1 Ack - 5 - W83194BR-730 PRELIMINARY AGPSEL=0 AGPSEL=1 (MHz) (MHz) 66 66.6 50 67 46.5 66 66.6 55 ...

Page 6

... W83194BR-730 PRELIMINARY PCI AGPSEL=0 AGPSEL=1 (MHz) (MHz) (MHz) 33.3 66.6 50 33.3 66 33.3 66.6 50 33.6 67.2 56 31.3 62 46.5 33.3 66.6 50 33.3 66 33.3 66 ...

Page 7

... W83194BR-730 PRELIMINARY PCI AGPSEL=0 AGPSEL=1 (MHz) (MHz) (MHz 34.33 68.67 51.5 34.67 69. 52 34.33 68.67 51.5 34.67 69.33 52 35.33 70.67 53 32.5 65 48.75 33 ...

Page 8

... SSEL1 ( Frequency table selection by software via I SSEL0 (Frequency table selection by software via Selection by hardware Selection by software Bit (7: Running 1 = Tristate all outputs Description 0: Free running pin Description Publication Release Date:Oct. 2000 - 8 - W83194BR-730 PRELIMINARY ...

Page 9

... CSkew0 (SDRAM to CPU skew program bit CAkew2 (AGP to CPU skew program bit CAkew1 (AGP to CPU skew program bit CAkew0 (AGP to CPU skew program bit 24_48MHz(Active / Inactive 48MHz(Active / Inactive) W83194BR-730 Description Description Description Publication Release Date:Oct. 2000 - 9 - PRELIMINARY Revision 0.60 ...

Page 10

... N value bit value bit value bit value bit value bit value bit value bit value bit 0 W83194BR-730 Description 0 = stop timer Description Description Publication Release Date:Oct. 2000 - 10 - PRELIMINARY Revision 0.60 ...

Page 11

... Register 11: Winbond Chip ID Register (Read Only) Bit @PowerUp Pin Winbond Chip Winbond Chip Winbond Chip Winbond Chip Winbond Chip Winbond Chip Winbond Chip Winbond Chip ID W83194BR-730 Description Description Description Publication Release Date:Oct. 2000 - 11 - PRELIMINARY Revision 0.60 ...

Page 12

... W83194BR-730 PRELIMINARY bit2 bit1 bit0 VCO/AGP AGP2 AGP1 AGP0 ratio ...

Page 13

... W83194BR-730 HOW TO READ THE TOP MARKING W83194BR-730 28051234 002GAB 1st line: Winbond logo and the type number: W83194BR-730 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 002: packages made in '00, week 02 G: assembly house ID ...

Page 14

... Winbond for any damages resulting from such improper use or sale. W83194BR-730 Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong ...

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