vsc8163 Vitesse Semiconductor Corp, vsc8163 Datasheet - Page 8

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vsc8163

Manufacturer Part Number
vsc8163
Description
Oc-48 16 1 Sonet/sdh Mux With Clock Generator
Manufacturer
Vitesse Semiconductor Corp
Datasheet

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Page 8
OC-48 16:1 SONET/SDH
MUX with Clock Generator
Table 1: AC Characteristics
Parameters
T
T
T
t
CLK16O
CLKI
RCK
CLKO
CLKO
CLK16O
t
t
Clock Multiplier Performance
T
T
Jitter
CLKR
SET
HOLD
DSU
DH
DOR
DJ
CJ
tol
D
,T
D
, t
D
PER
DOF
CLKF
D
PER
Data setup time to the rising
edge of CLK16I+
Data hold time after the
rising edge of CLK16+
DO± rise and fall time
CLK16O± rise and fall times
CLK16O± duty cycle
CLK16I± duty cycle
Reference clock duty cycle
CLKO duty cycle
CLKO period
CLK16O period
DO setup time with respect
to rising CLKO edge
DO hold time with respect to
rising CLKO edge
Output data jitter
Output clock jitter
Jitter tolerance
Tuning Range
Description
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
VITESSE
SEMICONDUCTOR CORPORATION
Min
0.75
-100
1.0
40
30
40
40
Internet: www.vitesse.com
401.9
Typ
310
6.4
90
Max
+100
120
250
60
70
60
60
4
4
Units
ppm
ns
ns
ps
ps
ps
ns
ps
ps
ps
ps
%
%
%
%
20% to 80% into 100 load
See Figure 6
See Figures 3 and 4
Assuming 10% distortion of CLKO
SONET based 77.76MHz or
155.52MHz reference clock
SONET based 77.76MHz or
155.52MHz reference clock
Inverting CLKO will switch (approx)
t
Inverting CLKO will switch (approx)
t
rms, tested to SONET specification
(12kHz to 20MHz) with 2ps rms jitter
on REFCLK.
rms, tested to SONET specification
(12kHz to 20MHz) with 2ps rms jitter
on REFCLK.
Exceeds SONET/SDH mask
SET
SET
and t
and t
Preliminary Data Sheet
HOLD
HOLD
Conditions
values.
values.
VSC8163
G52216-0, Rev 3.3
01/05/00

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