vsc8169 Vitesse Semiconductor Corp, vsc8169 Datasheet - Page 4

• Manufacturer Part Number: vsc8169
• Description: Oc-48 Fec 16 1 Sonet/sdh Mux With Clock Generator
• Manufacturer: Vitesse Semiconductor Corp

Page 4
MUX with Clock Generator
OC-48 (FEC) 16:1 SONET/SDH
High-Speed Data and Clock Output
sion line. The transmission line should be terminated with a 100 resistor at the load between true and comple-
ment outputs (see Figure 6). Connection to a termination voltage is not required. The output driver is back
terminated to 50 on-chip, providing a snubbing of any reflections. If used single-ended, the high-speed output
driver must still be terminated differentially at the load with a 100 resistor between true and complement out-
puts. The high-speed clock output can be powered down for additional power savings. To power down the high-
speed clock, tie the associated pins to V
Clock Generator
provided REFCLK input. The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscilla-
tor (VCO) with an on-chip loop filter. The loop bandwidth of the PLL is within the SONET specified limit of
2MHz.
An on-chip PLL generates the 2.48832GHz (or up to 2.7GHz for FEC) transmit clock from the externally
The high-speed data and clock output drivers consist of a differential pair designed to drive a 50 transmis-
VSC8169
Pre-Driver
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Figure 5: AC Termination of CLK16O+/-, REFCLKO+/-
50
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
Figure 6: High-Speed Output Termination
VITESSE
SEMICONDUCTOR CORPORATION
CC
V
V
EE
CC
(see Table 3, Package Pin Identifications, pins 5,6,7).
Z
Z
o
o
Internet: www.vitesse.com
50
50
50
V
CC
-2V
100nF
100nF
Z
0
= 50
Preliminary Data Sheet
downstream
100
bias point
generated
internally
VSC8169
G52230-0, Rev 3.6
01/02/01