vsc8169 Vitesse Semiconductor Corp, vsc8169 Datasheet
vsc8169
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vsc8169 Summary of contents
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... FIFO eliminating loop timing design issues by providing a flexible parallel timing architecture. The device operates using a 3.3V power supply, and is packaged in a thermally- enhanced plastic package. The thermal performance of the 128-pin PQFP allows the use of the VSC8169 with- out a heat sink under most thermal conditions. ...
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... The Upstream Device should use the CLK16O as the timing source for its final output latch (see Figure 1). The Upstream Device should then generate a CLK16I that is phase aligned with the data. The VSC8169 will latch D[15:0] ± on the rising edge of CLK16I+. The data must meet setup and hold times with respect to CLK16I (see Table 2) ...
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... Holding RESET constantly “low” bypasses the FIFO for transparent mode operation. Figure 3: Split-End DC Termination of CLK16O+/-, REFCLKO+/- VSC8169 Figure 4: Traditional DC Termination of CLK16O+/-, REFCLKO+/- VSC8169 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 G52230-0, Rev 3.6 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com ...
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... Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION (see Table 3, Package Pin Identifications, pins 5,6,7). CC Figure 6: High-Speed Output Termination Internet: www.vitesse.com Preliminary Data Sheet VSC8169 downstream 100nF bias point generated internally 100nF V -2V CC 100 G52230-0, Rev 3.6 01/02/01 ...
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... PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a VCXO may be required to avoid passing REFCLK noise with greater than 4ps RMS of jitter to the output. The VSC8169 will output the REFCLK noise in addition to the intrinsic jitter from the VSC8169 itself during such conditions. ...
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... OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator Supplies The VSC8169 is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to use the device in an ECL environment with a negative 3.3V supply, then V -3.3V. If used with V tied to -3.3V, the TTL control signals are still referenced Decoupling of the power supplies is a critical element in maintaining the proper operation of the part ...
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... Preliminary Data Sheet VSC8169 AC Characteristics Figure 9: Parallel Input Data and Clock Timing Waveform CLK16I+ Parallel Data Clock Input TXIN[0:15]+, TXPRTYIN Parallel Data Inputs CLK16O+ Parallel Data Clock Output Figure 10: Serial Data and Clock Output Phase Timing Waveform DO+ Differential Serial Data Output ...
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... Single = Ended Swing Differential = Swing ) is specified the single-ended swing. Internet: www.vitesse.com Preliminary Data Sheet VSC8169 Units Conditions ns ns 20% to 80% into 100 load ps See Figure 6 ps See Figures 3 and Assuming 10% distortion of CLKO % % SONET-based 77.76MHz or ps 155 ...
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... Preliminary Data Sheet VSC8169 Table 2: DC Characteristics Parameters Description V Output HIGH voltage (DO) OH(DO) V Output LOW voltage (DO) OL(DO) Data output differential voltage V OD(DO) (DO) CLK output differential voltage V OCLK(CLKO) (CLKO) V Output common-mode voltage CMO R Back termination impedance DO Output HIGH voltage (CLK16O REFCLKO±) ...
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... CC Operating Temperature Range ........................................................... 0 ESD Ratings Proper ESD procedures should be used when handling this product. The VSC8169 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V. Page 10 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • ...
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... VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 G52230-0, Rev 3.6 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com 01/02/01 VITESSE SEMICONDUCTOR CORPORATION Figure 13: Pin Diagram Top View—128-Pin PQFP VSC8169 Internet: www.vitesse.com OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator VCC 102 D13+ 101 D13– ...
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... Negative power supply GND Negative power supply — No connect, leave unconnected — No connect, leave unconnected — No connect, leave unconnected — No connect, leave unconnected Internet: www.vitesse.com Preliminary Data Sheet VSC8169 Description (1) (1) (1) for power down) CC for power down) CC for power down) CC (1) (1) ...
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... Preliminary Data Sheet VSC8169 Pin # Name I — — — 38 REF_FREQSEL I 39 VCC — 40 VEE — FIFO_WARN 42 VEE — 43 VCC — 44 RESET — — — — — 50 VCC — 51 VEE — 52 CLK16O ...
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... Negative power supply LVPECL Low-speed differential parallel data LVPECL Low-speed differential parallel data +3.3V Positive power supply LVPECL Low-speed differential parallel data LVPECL Low-speed differential parallel data +3.3V. Positive power supply +3.3V Positive power supply Internet: www.vitesse.com Preliminary Data Sheet VSC8169 Description G52230-0, Rev 3.6 01/02/01 ...
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... Preliminary Data Sheet VSC8169 Pin # Name I/O 104 NC — 105 D14- I 106 D14+ I 107 VCC — 108 D15- I 109 D15+ I 110 VEE — 111 NC — 112 NC — 113 NC — 114 NC — 115 NC — 116 REFCLK+ I 117 REFCLK- I 118 VCC — 119 VEE — ...
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... PQFP Package Drawing PIN 102 RAD. 2.92 .50 ( 2.54 .50 PIN TOP VIEW STANDOFF .25 b 0.17 MAX. LEAD COPLANARITY L Internet: www.vitesse.com Preliminary Data Sheet VSC8169 Key mm Tolerance A 2.35 MAX A1 0.25 MAX A2 2.00 +.10 D 17.20 ±.20 D1 14.00 ±.10 E 23.20 ±.20 E1 20.00 ±.10 L ...
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... Theta case-to-ambient at appropriate airflow CA Ambient air temperature A(MAX) Case temperature (85 C(MAX) P Power (1.7 W for VSC8169) (MAX) © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 G52230-0, Rev 3.6 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com 01/02/01 VITESSE SEMICONDUCTOR CORPORATION ...
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... Page 18 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION VSC8169 xx Package QR: 128PQFP, 14x20mm Body Internet: www.vitesse.com Preliminary Data Sheet VSC8169 G52230-0, Rev 3.6 01/02/01 ...