sy89202u Micrel Semiconductor, sy89202u Datasheet - Page 4

• Manufacturer Part Number: sy89202u
• Description: Sy89202u Precision 1 8 Lvpecl Fanout Buffer With Three ?1/ ?2/ ?4 Clock Divider Output Banks
• Manufacturer: Micrel Semiconductor

Pin Description
Truth Table
Notes:
1.
2.
3.
June 2006
10, 19, 22, 31
Pin Number
16, 15, 14,
30, 29, 28,
27, 26, 25,
13, 12, 11
/MR asynchronously forces Q0 – Q7 LOW (/Q0 - /Q7 HIGH).
EN forces Q0 – Q7 LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to “Timing Diagram” section.
EN synchronously enables the outputs between 2 and 6 input clock cycles after the rising edge of EN. Refer to “Timing Diagram” section.
1, 20, 21
2, 7, 8
24, 23
18, 17
/MR
3, 6
32
4
5
9
0
1
1
1
( 1)
Q4, /Q4, Q5, /Q5,
Q0, /Q0, Q1, /Q1,
Q2, /Q2, Q3, /Q3
Exposed Pad
Pin Name
VREF-AC
DIVSEL1
DIVSEL2
DIVSEL3
Q6, /Q6
Q7, /Q7
IN, /IN
EN
GND,
VCC
/MR
VT
EN
X
0
1
1
( 2, 3)
DIVSEL1
Pin Function
Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the
three banks of outputs. Note that each of these inputs is internally connected to a
25kΩ pull-up resistor and will default to logic HIGH state if left open. The input-
switching threshold is V
Differential Input: This input pair is the differential signal input to the device. This
input accepts AC- or DC-coupled signals as small as 100mV. The input pair
internally terminates to a VT pin through 50Ω. Note that these inputs will default to
an indeterminate state if left open. Please refer to the “Input Interface Applications”
section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates to
the VT pin. The VT pin provides a center-tap to a termination network for maximum
interface flexibility. See “Input Interface Applications” section for more details.
Reference Voltage: This output biases to V
inputs IN and /IN. For AC-coupled applications, connect V
pin. Bypass with 0.01µF low ESR capacitor to V
Single-Ended Input: This TTL/CMOS input disables and enables the Q0 – Q7
outputs. This input is internally connected to a 25kW pull-up resistor and will default
to logic HIGH state if left open. The input-switching threshold is V
enable and disable functional description, refer to “Timing Diagram” section.
Positive power supply. Bypass with 0.1uF//0.01uF low ESR capacitors as close to
VCC pins as possible.
Bank 2 LVPECL differential output pairs controlled by DIVSEL2: LOW, Q4 – Q6 =
÷2, HIGH, Q4 – Q6 = ÷4. Unused output pairs may be left open. Each output is
designed to drive 800mV into 50Ω terminated at V
Bank 1 LVPECL differential output pairs controlled by DIVSEL1: LOW, Q0 – Q3 =
÷1, HIGH, Q0 – Q3 = ÷2. Unused output pairs may be left open. Each output is
designed to drive 800mV into 50Ω terminated at V
Bank 3 LVPECL differential output pair controlled by DIVSEL3: LOW, Q7 = ÷2,
HIGH, Q7 = ÷4. Unused output pairs may be left open. Each output is designed to
drive 800mV into 50W terminated at V
Single-Ended Input: This TTL/CMOS-compatible master reset function
asynchronously sets Q0 – Q7 outputs LOW and /Q0 – /Q7 outputs HIGH, and holds
them in that state as long as the /MR input remains LOW. This input is internally
connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left
open. The input-switching threshold is V
Ground: Ground pin and exposed pad must be connected to the same ground
plane.
X
X
0
1
DIVSEL2
X
X
0
1
4
CC
DIVSEL3
/2.
X
X
0
1
CC
CC
–2V.
Q0 – Q3
/2.
CC
÷1
÷2
–1.2V. It is used for AC-coupling
0
0
[e-mail]
CC
.
CC
CC
–2V.
–2V.
REF-AC
Q4 – Q6
÷2
÷4
0
0
directly to the VT
CC
/2. For the input
M9999-061206-B
or [phone]
Q7
÷2
÷4
0
0