mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 34

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mt48h8m16lf

Manufacturer Part Number
mt48h8m16lf
Description
128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
Manufacturer
Micron Semiconductor Products
Datasheet

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Register Definition
Mode Register
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
There are two mode registers in the Mobile SDRAM component, the mode register and
the extended mode register (EMR). The mode register is illustrated in Figure 13 on
page 35. The mode register defines the specific mode of operation of the Mobile SDRAM,
including burst length (BL), burst type, CAS latency (CL), operating mode, and write
burst mode. The mode register is programmed via the LOAD MODE REGISTER
command and retains the stored information until it is programmed again or the device
loses power.
Mode register bits M[2:0] specify the BL, M3 specifies the type of burst, M4–M6 specify
the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and
M10 through Mn should be set to zero to ensure compatibility with future revisions.
Mn + 1and Mn + 2 should be set to zero to prevent the extended mode register from
being programmed.
The mode registers must be loaded when all banks are idle, and the controller must wait
t
will result in unspecified operation.
MRD before initiating the subsequent operation. Violating either of these requirements
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
Register Definition
Preliminary

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