mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 22

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

CLOCK SUSPEND
access/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
LOW, the next internal positive clock edge is sus-
pended. Any command or data present on the input
pins at the time of a suspended internal clock edge are
ignored; any data present on the DQ pins will remain
driven; and burst counters are not incremented as long
as the clock is suspended (see examples in Figures 22
and 23).
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
COMMAND
INTERNAL
ADDRESS
The clock suspend mode occurs when a column
For each positive clock edge on which CKE is sampled
Clock Suspend During WRITE Burst
NOTE: For this example, burst length = 4 or greater, and DQM
CLOCK
CLK
CKE
DQ
is LOW.
NOP
T0
BANK,
WRITE
COL n
T1
D
n
IN
Figure 22
T2
T3
NOP
n + 1
T4
D
IN
T5
NOP
n + 2
D
IN
22
HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
gramming the write burst mode bit (M9) in the Mode
Register to a logic 1. In this mode, all WRITE com-
mands result in the access of a single column location
(burst of one) regardless of the programmed burst
length. READ commands access columns according to
the programmed burst length and sequence, just as in
the normal mode of operation (M9 = 0).
COMMAND
INTERNAL
ADDRESS
CLOCK
Clock suspend mode is exited by registering CKE
The burst read/single write mode is entered by pro-
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
Clock Suspend During READ Burst
CKE
CLK
DQ
DQM is LOW.
T0
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BANK,
COL n
READ
T1
NOP
Figure 23
T2
NOP
D
OUT
n
T3
n + 1
D
OUT
T4
NOP
16Mb: x16
IT SDRAM
©1999, Micron Technology, Inc.
T5
NOP
n + 2
D
OUT
DON’T CARE
T6
NOP
D
n + 3
OUT