mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 17

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

truncated with, a PRECHARGE command to the same
bank (provided that AUTO PRECHARGE was not
activated) and a full-page burst may be truncated with
a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles be-
fore the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
A fixed-length READ burst may be followed by, or
COMMAND
COMMAND
COMMAND
NOTE: DQM is LOW.
ADDRESS
ADDRESS
ADDRESS
CLK
CLK
CLK
DQ
DQ
DQ
CAS Latency = 1
BANK a,
BANK a,
BANK a,
COL n
COL n
COL n
T0
T0
T0
READ
READ
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
T1
READ to PRECHARGE
NOP
NOP
NOP
D
OUT
n
T2
T2
T2
NOP
NOP
NOP
Figure 11
D
D
n + 1
OUT
OUT
n
17
T3
T3
T3
NOP
NOP
NOP
D
n + 2
D
D
n + 1
OUT
OUT
OUT
n
latency; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
that part of the row precharge time is hidden during
the access of the last data element(s).
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
PRECHARGE
PRECHARGE
PRECHARGE
(a or all)
(a or all)
(a or all)
T4
BANK
T4
BANK
T4
BANK
In the case of a fixed-length burst being executed to
X = 0 cycles
X = 1 cycle
D
n + 3
D
n + 2
D
n + 1
OUT
OUT
OUT
X = 2 cycles
T5
T5
T5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
NOP
NOP
D
n + 3
D
n + 2
OUT
OUT
t RP
t RP
t RP
T6
T6
T6
NOP
NOP
NOP
D
n + 3
OUT
DON’T CARE
BANK a,
BANK a,
BANK a,
ACTIVE
ACTIVE
ACTIVE
T7
T7
T7
ROW
ROW
ROW
16Mb: x16
IT SDRAM
t
RP is met. Note
©1999, Micron Technology, Inc.