cy7c1386b-cy7c1387b Cypress Semiconductor Corporation., cy7c1386b-cy7c1387b Datasheet - Page 11

• Manufacturer Part Number: cy7c1386b-cy7c1387b
• Description: 512k X 36/1m X 18 Pipelined Dcd Sram
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-05195 Rev. **
Write Cycle Descriptions
Notes:
5.
6.
7.
Read
Read
Write Byte 0 - DQa
Write Byte 1- DQb
Write Bytes 1, 0
Write Byte 2 - DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 - DQd5
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
Write All Bytes
Read
Read
Write Byte 0 - DQ
Write Byte 1 - DQ
Write All Bytes
Write All Bytes
X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW.
The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is a
“don't care” for the remainder of the Write cycle.
OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive
or when the device is deselected, and DQ = data when OE is active.
Function (1386B)
Function (1387B)
[7:0]
[15:8]
and DP
and DP
0
1
[5,6,7]
GW
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
GW
1
1
1
1
1
0
BWE
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BWE
X
1
0
0
0
0
BWd
X
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
x
. Writes may occur only on subsequent clocks after
BWc
X
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
BWb
X
X
1
1
0
0
BWb
X
X
CY7C1386B
CY7C1387B
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
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BWa
X
X
1
0
1
0
BWa
X
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0