s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 203

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

TOVx — Toggle-On-Overflow Bit
CHxMAX — Channel x Maximum Duty Cycle Bit
18.8.5 TIMA Channel Registers
These read/write registers contain the captured TIMA counter value of the input capture function or the
output compare value of the output compare function. The state of the TIMA channel registers after reset
is unknown.
In input capture mode (MSxB–MSxA = 0:0) reading the high byte of the TIMA channel x registers
(TACHxH) inhibits input captures until the low byte (TACHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0) writing to the high byte of the TIMA channel x registers
(TACHxH) inhibits output compares and the CHxF bit until the low byte (TACHxL) is written.
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When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIMA counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As
it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is
cleared.
1 = Channel x pin toggles on TIMA counter overflow.
0 = Channel x pin does not toggle on TIMA counter overflow.
Register Name and Address
PTEx/TCHx
When TOVx is set, a TIMA counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX
Reset:
Read:
Write:
OVERFLOW
Bit 15
Bit 7
COMPARE
PERIOD
OUTPUT
(TACH0H/L–TACH5H/L) (Sheet 1 of 3)
Bit 14
Figure 18-9. TIMA Channel Registers
6
MC68HC908AZ32A Data Sheet, Rev. 2
Figure 18-8. CHxMAX Latency
OVERFLOW
TACH0H — $0027
Figure 18-8
Bit 13
5
COMPARE
OUTPUT
Indeterminate after Reset
NOTE
Bit 12
OVERFLOW
4
shows, the CHxMAX bit takes effect in the cycle after
Bit 11
COMPARE
OUTPUT
3
OVERFLOW
Bit 10
2
COMPARE
OUTPUT
Bit 9
1
OVERFLOW
Bit 0
Bit 8
I/O Registers
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