s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 176

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Serial Peirpheral Interface (SPI)
17.7 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests:
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU
interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt,
provided that the SPI is enabled (SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF flags to generate a
receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF
flag is enabled to generate receiver/error CPU interrupt requests.
Two sources in the SPI status and control register can generate CPU interrupt requests:
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1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift
2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the
register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate an SPI receiver/error CPU interrupt request.
transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
SPTE (Transmitter Empty)
SPRF (Receiver Full)
OVRF (Overflow)
MODF (Mode Fault)
ERRIE
MODF
OVRF
Flag
Figure 17-9. SPI Interrupt Request Generation
SPRIE
SPTE
MC68HC908AZ32A Data Sheet, Rev. 2
Table 17-3. SPI Interrupts
SPTIE
SPRF
SPI Transmitter CPU Interrupt Request (SPTIE = 1)
SPI Receiver CPU Interrupt Request (SPRIE = 1)
SPI Receiver/Error Interrupt Request
(SPRIE = 1, ERRIE = 1)
SPI Receiver/Error Interrupt Request
(SPRIE = 1, ERRIE = 1, MODFEN = 1)
SPE
Request
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
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