s908qc16g0cdte Freescale Semiconductor, Inc, s908qc16g0cdte Datasheet - Page 43

• Manufacturer Part Number: s908qc16g0cdte
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

3.8.4 ADC10 Clock Register (ADCLK)
This register selects the clock frequency for the ADC10 and the modes of operation.
ADLPC — ADC10 Low-Power Configuration Bit
ADIV[1:0] — ADC10 Clock Divider Bits
ADICLK — Input Clock Select Bit
MODE[1:0] — 10- or 8-Bit or Hardware Triggered Mode Selection
Freescale Semiconductor
ADLPC controls the speed and power configuration of the successive approximation converter. This
is used to optimize power consumption when higher sample rates are not required.
ADIV1 and ADIV0 select the divide ratio used by the ADC10 to generate the internal clock ADCK.
Table 3-3
If ACLKEN is clear, ADICLK selects either the bus clock or an alternate clock source as the input clock
source to generate the internal clock ADCK. If the alternate clock source is less than the minimum
clock speed, use the internally-generated bus clock as the clock source. As long as the internal clock
ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency (f
the minimum and maximum clock speeds (considering ALPC), correct operation can be guaranteed.
These bits select 10- or 8-bit operation. The successive approximation converter generates a result
that is rounded to 8- or 10-bit value based on the mode selection. This rounding process sets the
transfer function to transition at the midpoint between the ideal code voltages, causing a quantization
error of ± 1/2
Reset returns 8-bit mode.
1 = Low-power configuration: The power is reduced at the expense of maximum clock speed.
0 = High-speed configuration
1 = The internal bus clock is selected as the input clock source
0 = The alternate clock source IS SELECTED
00 = 8-bit, right-justified, ADCSC software triggered mode enabled
01 = 10-bit, right-justified, ADCSC software triggered mode enabled
10 = Reserved
11 = 10-bit, right-justified, hardware triggered mode enabled
shows the available clock configurations.
Reset:
Read:
Write:
LSB
.
ADLPC
Bit 7
0
ADIV1
0
0
1
1
Figure 3-7. ADC10 Clock Register (ADCLK)
ADIV1
6
0
Table 3-3. ADC10 Clock Divide Ratio
MC68HC08QY/QT Family Data Sheet, Rev. 2
ADIV0
0
1
0
1
ADIV0
5
0
Divide Ratio (ADIV)
ADICLK
0
4
1
2
4
8
MODE1
3
0
MODE0
Input clock ÷ 1
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
2
0
Clock Rate
ADLSMP
1
0
ACLKEN
Bit 0
0
ADCK
) between
Registers
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