z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 342

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
Clock Selection Following System Reset
Clock Failure Detection and Recovery
Unintentional access to the Oscillator Control register (OSCCTL) stops the chip by
switching to a non-functioning oscillator. Accidental alteration of the OSCCTL register is
prevented by a locking/unlocking scheme. To write the register, unlock it by making two
writes to the OSCCTL register with the values
OSCCTL register then changes the value of the register and returns the register to a locked
state. Any other sequence of oscillator control register writes has no effect. The values
written to unlock the register must be ordered correctly, but need not be consecutive. It is
possible to access other registers within the locking/unlocking operation.
The internal precision oscillator is selected following a System Reset. Startup code after
the System Reset changes the system clock source by unlocking and configuring the
OSCCTL register. If the
Low Power mode is enabled during reset. When Flash Low Power mode is enabled during
reset, the
field of the OSCDIV register will be set to
Primary Oscillator Failure
The ZNEO Z16F Series generates a System Exception when a failure of the primary
oscillator occurs if the
function in this situation, the clock failure recovery circuitry automatically forces the
Watchdog Timer oscillator to drive the system clock. Although this oscillator runs at a
much lower frequency than the original system clock, the CPU continues to operate,
allowing execution of a clock failure vector and software routines that either remedy the
oscillator failure or issue a failure alert. This automatic switch-over is not available if the
WDT is the primary oscillator.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1 kHz ±50%. For operating frequencies below 2 kHz, do not enable the clock
failure circuitry (
Watchdog Timer Failure
In the event of a Watchdog Timer oscillator failure, a System Exception is used if the
WDFEN
switch-over, but alerts the CPU of the failure. After a WDT failure, it is no longer possible
to detect a primary oscillator failure.
The Watchdog Timer oscillator failure detection circuit counts system clocks while
looking for a WDT clock. The logic counts 8000 system clock cycles before determining
that a failure occurred. The system clock rate determines the speed at which the WDT
failure is detected. A very slow system clock results in very slow detection times.
bit of the OSCCTL register is set. This event does not trigger an attendant clock
FLPEN
bit in the
POFEN
POFEN
must be deserted in the OSCCTL register).
LPOPT
Oscillator Control Register (OSCCTL)
P R E L I M I N A R Y
bit is set in the OSCCTL register. To maintain system
bit in
Program Memory Address 0003H
08H
E7H
.
followed by
Product Specification
18H
will be set and the
ZNEO
. A third write to the
Oscillator Control
is zero, Flash
™
Z16F Series
DIV
328