z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 209
z16f2811
Manufacturer Part Number
z16f2811
Description
High Performance Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z16F2811.pdf
(383 pages)
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Table 103. ESPI State Register (ESPISTATE)
PS022006-0207
RESET
FIELD
ADDR
BITS
R/W
ESPI State Register
SCKI
R
7
0
TFST—Transfer Status
0 = No data transfer is currently in progress.
1 = Data transfer is currently in progress.
SLAS—Slave Select
Reading this bit returns the current value of the SS exclusive-OR’d with the SSPO bit.
0 = SS pin is low, if SSPO = 0, SS pin is high if SSPO = 1 (SS is asserted).
1 = SS pin is high, if SSPO = 0, SS pin is low if SSPO = 1 (SS is deasserted).
The ESPI State register (see
internal state.
SCKI—Serial Clock Input
This bit reflects the state of the serial clock pin.
0 = The SCK input pin is low
1 = The SCK input pin is high
SDI—Serial Data Input
This bit reflects the state of the serial data input (MOSI or MISO depending on the
bit).
0 = The serial data input pin is low.
1 = The serial data input pin is high.
ESPISTATE—ESPI State Machine
Indicates the current state of the internal ESPI State Machine. This information is intended
for manufacturing test. The state values may change in future hardware revisions and are
not intended to be used by a software driver.
states.
SDI
R
6
0
5
P R E L I M I N A R Y
Table
103) provides observability of the ESPI clock, data, and
4
FF_E265H
Table 104
3
ESPISTATE
Enhanced Serial Peripheral Interface
R
0
on page 196 defines the valid
2
Product Specification
ZNEO
1
™
Z16F Series
MMEN
0
195
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