mma1605wr2 Freescale Semiconductor, Inc, mma1605wr2 Datasheet - Page 38

• Manufacturer Part Number: mma1605wr2
• Description: Dsi Inertial Sensor
• Manufacturer: Freescale Semiconductor, Inc

38
MMA16xxWR
Table 39. OTP Register Nibble Address Assignments
Bnk[1] Bnk[0] WA[3]
Bank Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
x
x
x
x
x
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
Register Address (Nibble)
WA[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
WA[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
WA[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DEVCFG1[3:0]
DEVCFG2[3:0]
DEVCFG1[7:4]
DEVCFG[3:0]
DEVCFG[7:4]
DEVCFG2[7]
DEVCFG2[5]
DEVCFG2[6]
DEVCFG2[4]
TYPE[7:6]
UD01[3:0]
UD02[3:0]
UD03[3:0]
UD04[3:0]
UD05[3:0]
UD06[3:0]
UD07[3:0]
UD08[3:0]
UD01[7:4]
UD02[7:4]
UD03[7:4]
UD04[7:4]
UD05[7:4]
UD06[7:4]
UD07[7:4]
UD08[7:4]
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
Register
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
RD[3] is written to the DEVID bit, RD[2:0] is written to DEVCFG[6:4] - UNUSED
RD[3] is written to DEVCFG[3] - UNUSED, RD[2:0] is written to CRC_U[2:0]
RD[3:2] is written to UD00[1:0], RD[1:0] is written to AT[1:0]
Only RD[2] is written to the DEVCFG2[6] bit (UNUSED)
Only RD[3] is written to the LOCK_U bit
Only RD[0] is written to DEVCFG2[4]
Only RD[1] is written to the PCM bit
Only RD[3:2] is written to LPF[1:0]
RD[3:0] is written to ADDR[3:0]
RD[3:0] is written to UD01[3:0]
RD[3:0] is written to UD02[3:0]
RD[3:0] is written to UD03[3:0]
RD[3:0] is written to UD04[3:0]
RD[3:0] is written to UD05[3:0]
RD[3:0] is written to UD06[3:0]
RD[3:0] is written to UD07[3:0]
RD[3:0] is written to UD08[3:0]
RD[3:0] is written to UD00[5:2]
RD[3:0] is written to UD01[7:4]
RD[3:0] is written to UD02[7:4]
RD[3:0] is written to UD03[7:4]
RD[3:0] is written to UD04[7:4]
RD[3:0] is written to UD05[7:4]
RD[3:0] is written to UD06[7:4]
RD[3:0] is written to UD07[7:4]
RD[3:0] is written to UD08[7:4]
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