mma1605wr2 Freescale Semiconductor, Inc, mma1605wr2 Datasheet - Page 35

• Manufacturer Part Number: mma1605wr2
• Description: Dsi Inertial Sensor
• Manufacturer: Freescale Semiconductor, Inc

4.2.1.5
of ‘0000’. The data bits D[7:0] in the command are only used in the CRC calculation.
Table 28. Request ID Information Command Bit Definitions
4.2.1.6
4.2.1.7
Sensors
Freescale Semiconductor
Table 27. Request ID Information Command
Table 30. Long Response - Request ID Information Command
D[15]
D[7]
A[3]
The Request ID Information command is supported in the following command formats:
The device ignores the Request ID Information command if the DSI device address is set to the DSI Global Device Address
Table 31. Request ID Response Bit Definitions
DSI Command ‘0101’ is not implemented. The device ignores all command formats with a command ID of ‘0101’.
DSI Command ‘0110’ is not implemented. The device ignores all command formats with a command ID of ‘0110’.
⎯
Table 29. Short Response - Request ID Information Command
Bit Field
D[14]
D[4:0] = {1’b0,DEVID, 3’b100}
C[3:0]
A[3:0]
D[7:0]
0
D[14]
D[6]
A[2]
⎯
D[13]
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference
• Enhanced Short Command as configured by the Format Control Command (Reference
Bit Field
0
Request ID Information Command
DSI Command #5
DSI Command #6
V[2:0]
A[3:0]
D[13]
D[5]
A[1]
⎯
Request ID Information Data Command = ‘0100’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
Used for CRC calculation only
D[12]
0
D[12]
D[4]
A[0]
⎯
D[11]
Data
0
D[11]
D[3]
⎯
0
D[10]
Device Identifier:‘00100’, or ‘01100’
DEVID: Bit 7 of the DEVCFG regIster
Version ID. This field indicates the device / silicon revision of the device.
DSI device address. This field contains the device address.
Shaded bits are transmitted to meet the response message length of the received message
0
D[10]
D[2]
⎯
0
D[9]
0
D[1]
D[9]
⎯
0
D[8]
0
D[0]
D[8]
Response
Response
⎯
0
D[7]
V2
A[3]
D[7]
A[3]
V[2]
D[6]
V1
A[2]
D[6]
A[2]
V[1]
Definition
Address
D[5]
V0
Definition
A[1]
D[5]
A[1]
V[0]
D[4]
0
A[0]
D[4]
A[0]
0
DEVID
D[3]
DEVID
C[3]
D[3]
0
D[2]
1
C[2]
D[2]
Command
1
1
D[1]
0
Section 4.2.1.11
Section 4.2.1.11
C[1]
D[1]
0
0
D[0]
0
C[0]
D[0]
0
0
MMA16xxWR
0 to 8 bits
)
)
CRC
0 to 8 bits
0 to 8 bits
CRC
CRC
35