mma1605wr2 Freescale Semiconductor, Inc, mma1605wr2 Datasheet - Page 37

• Manufacturer Part Number: mma1605wr2
• Description: Dsi Inertial Sensor
• Manufacturer: Freescale Semiconductor, Inc

Table 35. Write NVM Command Bit Definitions
Table 38. Write NVM Response Bit Definitions
4.2.1.10
DSI Global Device Address of ‘0000’.
NV bit is cleared when the command is executed, the mirror registers addressed by WA[3:0] are updated with the contents of
RD[3:0] and the DSI Device Address is returned regardless of the WA[3:0] value. If the Write NVM command is a request to
change the Device Address, the new Device Address is returned.
the VPP voltage is completed while writing is in process. To verify proper writes, it is recommend that the registers be read back
after writes to verify proper contents. The total Execution time for the Write NVM command is t
being programmed (1 - 4 bits). Inter-frame spacing between the Write NVM command and the subsequent DSI command must
accommodate this timing.
change to the CRC calculation regardless of the state of the NV bit and the LOCK_U bit. A CRC mismatch will only be detected
if the LOCK_U bit is active (reference
Sensors
Freescale Semiconductor
Table 34. Write NVM Command
Bit Field
Table 36. Long Response - Write NVM Command (NV = 1)
Table 37. Long Response - Write NVM Command (NV = 0)
Bit Field
Bnk[1:0]
WA[3:0]
WA[3:0]
RD[3:0]
D[15]
D[15]
RD[3:0]
WA[3]
D[7]
C[3:0]
A[3:0]
A[3:0]
A[3]
A[3]
The Write NVM command is supported in the following command formats:
The device ignores the Write NVM command if the command is in any other format, or if the DSI device address is set to the
The Write NVM command uses the nibble address definitions in
Writes to OTP occur only if the NV bit is set. The NV bit is set by the Initialization Command (reference
The DSI Bus idle voltage must exceed the minimum V
Writes to the User Programmable OTP array using the Write NVM Command will update the mirror registers and result in a
D[14]
D[14]
WA[2]
D[6]
A[2]
A[2]
Write NVM Command = ‘1001’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is
ignored.
RD[3:0] contains the data to be written to the OTP location addressed by WA[3:0] when the NV bit is set.
WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set.
These bits provide the bank address selected in the Initialization command.
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is
ignored.
RD[3:0] contains the contents of the registers addressed by WA[3:0] after the execution of the NVM write.
WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set.
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference
Write NVM Command
D[13]
D[13]
WA[1]
D[5]
A[1]
A[1]
WA[0]
D[12]
D[12]
D[4]
A[0]
A[0]
Data
D[11]
D[11]
WA[3]
RD[3]
D[3]
0
D[10]
WA[2]
D[10]
RD[2]
Section
D[2]
0
WA[1]
RD[1]
D[1]
D[9]
D[9]
3.2.2).
0
WA[0]
RD[0]
D[0]
D[8]
D[8]
0
PP
Data
Data
voltage when programming the OTP array. No internal verification of
A[3]
D[7]
D[7]
A[3]
1
1
Definition
Definition
Table 2
A[2]
D[6]
D[6]
A[2]
1
1
Address
Bnk[1]
A[1]
D[5]
D[5]
and summarized in
A[1]
1
Bnk[0]
A[0]
D[4]
D[4]
A[0]
1
RD[3]
C[3]
D[3]
D[3]
A[3]
1
PROG_BIT
Table
RD[2]
C[2]
D[2]
D[2]
A[2]
Command
0
39.
Section
times the number of bits
RD[1]
C[1]
D[1]
D[1]
A[1]
Section
0
RD[0]
4.2.1.11)
C[0]
D[0]
D[0]
A[0]
1
4.2.1.1). If the
MMA16xxWR
0 to 8 bits
0 to 8 bits
0 to 8 bits
CRC
CRC
CRC
37