sca100t VTI Hamlin, sca100t Datasheet - Page 10

• Manufacturer Part Number: sca100t
• Description: The Sca100t Dual Axis Inclinometer Series
• Manufacturer: VTI Hamlin

2.3 Ratiometric Output
2.4 SPI Serial Interface
VTI Technologies Oy
www.vti.fi
Figure 9.
Ratiometric output means that the zero offset point and sensitivity of the sensor are proportional to
the supply voltage. If the SCA100T supply voltage is fluctuating the SCA100T output will also vary.
When the same reference voltage for both the SCA100T sensor and the measuring part (A/D-
converter) is used, the error caused by reference voltage variation is automatically compensated
for.
A Serial Peripheral Interface (SPI) system consists of one master device and one or more slave
devices. The master is defined as a micro controller providing the SPI clock and the slave as any
integrated circuit receiving the SPI clock from the master. The ASIC in VTI Technologies’ products
always operates as a slave device in master-slave operation mode.
The SPI has a 4-wire synchronous serial interface. Data communication is enabled by a low active
Slave Select or Chip Select wire (CSB). Data is transmitted by a 3-wire interface consisting of
wires for serial data input (MOSI), serial data output (MISO) and serial clock (SCK).
The SPI interface in VTI products is designed to support any micro controller that uses SPI bus.
Communication can be carried out by either a software or hardware based SPI. Please note that in
the case of hardware based SPI, the received acceleration data is 11 bits. The data transfer uses
the following 4-wire interface:
MOSI
MISO
SCK
CSB
Each transmission starts with a falling edge of CSB and ends with the rising edge. During
transmission, commands and data are controlled by SCK and CSB according to the following
rules:
•
•
commands and data are shifted; MSB first, LSB last
each output data/status bits are shifted out on the falling edge of SCK (MISO line)
MICROCONTROLLER
SERIAL CLOCK (SCK)
DATA OUT (MOSI)
Typical SPI connection
DATA IN (MISO)
MASTER
master out slave in
master in slave out
serial clock
chip select (low active)
SS0
SS1
SS2
SS3
Subject to changes
Doc. nr. 8261800
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SLAVE
µP → SCA100T
µP → SCA100T
µP → SCA100T
SCA100T → µP
SCA100T Series
Rev.A
10/18