tm1300 NXP Semiconductors, tm1300 Datasheet - Page 340

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
fmulflags
SYNTAX
FUNCTION
DESCRIPTION
and stores a bit vector representing the exception flags into r dest . The argument values are in IEEE single-precision
floating-point format; the result is an integer bit vector. The bit vector stored in r dest has the same format as the IEEE
exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is according
to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted before computing the
product, and the IFZ bit in the result is set. If the product would be denormalized, the OFZ bit in the result is set.
modification of the destination register. If the LSB of r guard is 1, r dest is written; otherwise, r dest is not changed.
EXAMPLES
A-54
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38)
r41 = 0x3f000000 (0.5),
r80 = 0x00800000 (1.17549435e–38)
r42 = 0x7f800000 (+INF),
r43 = 0x0 (0.0)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
r82 = 0x00c00000 (1.763241526e–38),
r83 = 0x8080000 (–1.175494351e–38)
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (–INF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00800000 (1.763241526e–38)
The
The
[ IF r guard ] fmulflags r src1 r src2
if r guard then
fmulflags
fmulflags
r dest
31
0
Initial Values
ieee_flags((float)r src1
operation computes the IEEE exceptions that would result from computing the product r src1 r src2
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls the
PRODUCT SPECIFICATION
(float)r src2 )
fmulflags r60 r30
fmulflags r40 r60
IF r10 fmulflags r40 r80
IF r20 fmulflags r40 r80
fmulflags r41 r80
fmulflags r42 r43
fmulflags r40 r81
fmulflags r82 r83
fmulflags r84 r85
fmulflags r70 r70
fmulflags r80 r80
IEEE status flags from floating-point multiply
r dest
Operation
7
0
OFZ
r90
r95
r110
r106
r111
r112
r113
r120
r125
6
IFZ
5
r100
r105
INV
4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
fmul faddflags readpcsw
r90
r95
no change, since guard is false
r105
r110
r106
r111
r112
r113
r120
r125
OVF
3
Philips Semiconductors
0
0
UNF
0
0x46 (OFZ UNF INX)
0x10 (INV)
0x20 (IFZ)
0x06 (UNF INX)
0
0x0a (OVF INX)
0x06 (UNF INX)
ATTRIBUTES
2
SEE ALSO
Result
INX
1
DBZ
0
ifmul
143
2, 3
No
—
2
3