sg25672rddr6h2bgic ETC-unknow, sg25672rddr6h2bgic Datasheet - Page 19

• Manufacturer Part Number: sg25672rddr6h2bgic
• Description: Dram Module Ddr Sdram 2gbyte 184rdimm
• Manufacturer: ETC-unknow

Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Inputs are not recognized as valid until V
11. CK and CK# slew rates are
AC Output Load Circuit Diagram
Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:[phone] • Fax:[phone] • E-mail: [e-mail]
Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: [phone] • Fax: [phone]
Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: [phone] • Fax: [phone]
Maximum burst refresh of 8.
The specific requirement is that DQS be valid(HIGH or LOW) on or before this CK edge. A valid transition is defined as monotonic
and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be
transitioning from High-Z to logic low. If a previous write was in progress, DQS could be HIGH, LOW or transitioning from HIGH to
LOW at this time, depending on t
The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter but sys-
tem performance (bus turnaround) will degrade accordingly.
A write command can be applied with t
Min(t
These parameters guarantee device timing, but they are not necessarily tested on each device.
t
a specific voltage level but specify when the device output is no longer driving (HZ) or begins driving (LZ).
t
sists of t
channel to n-channel variation of the output drivers.
The CK/CK# input reference level (for timing reference to CK/CK#) is the point at which CK and CK# cross. The input reference
level for signals other than CK and CK# is V
HZ
QH
, and t
= t
CL
HP
,t
DQSQ
CH
LZ
- X, where t
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device.
transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to
(max), the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-
Output
(V
OUT
HP
)
= minimum half clock period for any given cycle and is defined by clock high or clock low (t
≥
1.0V/ns.
DQSS
V
.
RCD
TT
REF
50Ω
30pF
satisfied after this command.
REF
stabilizes.
.
Timing Reference Point
SG25672RDDR6H2BGUU
July 5, 2007
CL
,t
CH
). X con-
19