sg25672rddr6h2bgic ETC-unknow, sg25672rddr6h2bgic Datasheet
sg25672rddr6h2bgic
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sg25672rddr6h2bgic Summary of contents
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... Part Numbers Description SG25672RDDR6H2BGIC 256Mx72 (2GB), DDR, 184-pin DIMM, Registered, ECC, 128Mx4 Based, PC2700, DDR333B, 30.48mm, 18Ω DQ termination, Green Module (RoHS Compliant). SG25672RDDR6H2BGSC 256Mx72 (2GB), DDR, 184-pin DIMM, Registered, ECC, 128Mx4 Based, PC2700, DDR333B, 30.48mm, 18Ω DQ termination, Green Module (RoHS Compliant). ...
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... July 5, 2007 Changed datasheet part number from SG25672RDDR6H2BGSC to SG25672RDDR6H2BGUU because of the addition of a new device vendor. Added SG25672RDDR6H2BGIC to the Ordering Information on page 1. • December 27, 2004 Datasheet released. Corporate Headquarters Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • ...
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DDR SDRAM Module - 128Mx4 Based Features • Standard : JEDEC • Configuration : ECC • Cycle Time : 6.0ns • CAS# Latency : 2.0, 2.5 • Burst Length : • Burst Type : Sequential/Interleave ...
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Pin Description Table Symbol Type Polarity CK0 SSTL Positive Edge CK0# SSTL Negative Edge CKE0, CKE1 SSTL Active High CS0#, CS1# SSTL Active Low RAS#, CAS#, SSTL Active Low WE# BA0, BA1 SSTL - A0~A9, SSTL - A10/AP, A11~A12 DQ0~DQ63 ...
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Block Diagram RCS0# RCS1# RCKE0 RCKE1 18Ω DQS0 DQS S# CKE DQS S# CKE 18Ω DQ0 I/O 0 I/O 0 18Ω DQ1 I/O 1 I/O 1 U04 18Ω DQ2 I/O 2 I/O 2 18Ω I/O 3 I/O 3 DQ3 18Ω ...
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U1 22Ω CS0# E RCS0 (U00, U01, U04, U05, U08, U09, U12, U13, U16, U17, U20, U21, U24, U25, U28, U29, U32, U33) G CS1# RCS1 (U02, U03, U06, U07, U10, U11, ...
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Physical Dimensions 184-pin DIMM Module 1 2.30 6.35 6.35 R0. 1.80±0.10 2.175 Detail A (All dimensions are in millimeters with ±0.15mm tolerance unless specified otherwise.) Corporate Headquarters Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 ...
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Serial Presence Detect Table (SG2567RDDR6H2BGIC/SC) Byte No. Byte Description bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type row address on this ...
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Serial Presence Detect Table (Contd.) Byte No. Byte Description 27 Minimum row precharge time (=tRP) 28 Minimum row active to row active delay (=tRRD) 29 Minimum RAS to CAS delay (=tRCD) 30 Minimum activate precharge time (=tRAS) 31 Module row ...
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Serial Presence Detect Table (Contd.) Byte No. Byte Description 93 Manufacturing data (Year) 94 Manufacturing data (Week) 95~98 Assembly serial # 99~125 Manufacturer specific data 126~127 Unused storage locations 128~255 Unused storage locations Note: 1. Manufacturing Location: 00h - Undefined, ...
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Mode Register Table Definition The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as ...
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Extended Mode Register Table Definition The Extended Mode Register is used to control functions beyond those controlled by Mode Register. This definition includes DLL Enable/Disable, Output Drive Strength, and QFC Enable/Disable as shown in table below. The Mode Register is ...
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Commands The following Truth Tables provide a general reference of available commands. For a more detailed description please refer to the device data sheets. Truth Table - Commands Name (Function) Deselect (NOP) No Operation (NOP) Active (Select bank and activate ...
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Absolute Maximum Ratings Parameter Voltage on any pin relative to V Voltage on V relative Voltage on V relative to V DDQ SS Voltage on V relative to V DDSPD Power Dissipation Operating Temperature Storage Temperature ...
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Capacitance (V = 2.5V±0.2V +25° 1MHz Parameter Input Capacitance (Address & Control) Input Capacitance (CK0, CK0#) Input Capacitance (DQS0~DQS17) Input/Output Capacitance (DQ0~DQ63, CB0~CB7 2.5V±0.2V 0V Parameter Input ...
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DC Characteristics (Contd 2.5V±0.2V 0V Parameter OPERATING CURRENT: One Bank; Active-Precharge; tRC = tRC MIN; tCK = tCK MIN; DQ, DM and DQS inputs chang- ing twice per clock cyle; address and control ...
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Parameter Row Cycle Time Refresh row cycle time Row active time RAS# to CAS# delay Row precharge time Row active to Row active delay Write recovery time Internal write to read command delay Clock cycle time CL=2.0 CL=2.5 Clock high ...
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Device AC Characteristics (Cont’d) Parameter Mode register set cycle time Address and Control Input setup time Address and Control Input hold time DQ & DM setup time to DQS DQ & DM hold time to DQS DQS-in high level width ...
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Notes: 1. Maximum burst refresh The specific requirement is that DQS be valid(HIGH or LOW before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the ...
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Disclaimer: No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of SMART Modular Technologies, Inc. (“SMART”). The ...