sg25672rddr6h2bgic ETC-unknow, sg25672rddr6h2bgic Datasheet - Page 11
sg25672rddr6h2bgic
Manufacturer Part Number
sg25672rddr6h2bgic
Description
Dram Module Ddr Sdram 2gbyte 184rdimm
Manufacturer
ETC-unknow
Datasheet
1.SG25672RDDR6H2BGIC.pdf
(20 pages)
Mode Register Table Definition
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of
a burst length, a burst type, a CAS latency, and an operating mode, as shown in the table below. The Mode Register is pro-
grammed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is
programmed again or the device loses power (except for bit A8, which is self-clearing). In the table below, note that n = 11 for
128Mb devices, n = 12 for 256Mb and 512Mb devices, and n = 13 for 1Gb devices.
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Address Bus
Mode Register
Bits
Mn+2
BA1
0
Mn+1
BA0
0
Mn
0
0
..
0
0
Mn
An
..
0
0
..
..
Operating Mode
M9
0
0
..
..
M8
M9
A9
0
1
M7
M8
A8
0
0
Normal Operation
Reset DLL
M7
M6
A7
Operating Mode
0
1
SG25672RDDR6H2BGUU
M6
M5
A6
1
1
CAS Latency
M5
M4
A5
0
0
M4
A4
CAS Latency
M3
0
1
2.0
2.5
M3
A3
BT
M2
Burst Type
Sequential
Interleave
0
0
0
M2
A2
Burst Length
M1
0
1
1
M1
A1
July 5, 2007
M0
1
0
1
M0
A0
Length
Burst
2
4
8
11