sg2567udr212851hc ETC-unknow, sg2567udr212851hc Datasheet - Page 4
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sg2567udr212851hc
Manufacturer Part Number
sg2567udr212851hc
Description
Dram Module Ddr2 Sdram 2gbyte 240udimm
Manufacturer
ETC-unknow
Datasheet
1.SG2567UDR212851HC.pdf
(26 pages)
DDR2 240-pin DIMM Pin List (Contd.)
Pin Description Table
Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
Pin
No.
21
22
23
24
25
26
27
28
29
30
Symbol
CK0~CK2
CK0#~CK2#
ODT0, ODT1
CKE0, CKE1
CS0#, CS1#
RAS#, CAS#,
WE#
BA0~BA2
Pin
Name
DQ10
DQ11
V
DQ16
DQ17
V
DQS2#
DQS2
V
DQ18
SS
SS
SS
Pin
No.
51
52
53
54
55
56
57
58
59
60
Type
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
Pin
Name
V
CKE0
V
BA2
NC
V
A11
A7
V
A5
DDQ
DD
DDQ
DD
Polarity
Positive Edge
Negative Edge
Active High
Active High
Active Low
Active Low
-
Pin
No.
81
82
83
84
85
86
87
88
89
90
Pin
Name
DQ33
V
DQS4#
DQS4
V
DQ34
DQ35
V
DQ40
DQ41
SS
SS
SS
Function
Positive line of the differential pair of system clock inputs. (All DDR2 SDRAM address and
control inputs are sampled on the rising edge of their associated clocks. Output data is ref-
erenced at the crossings of the clocks.)
Negative line of the differential pair of system clock inputs.
On-Die Termination: ODT when high enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, and
DM. The ODT input will be ignored if disabled in Extended Mode Register (EMRS).
Activates the DDR2 SDRAM CLK signal when high and deactivates the CLK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self
Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables
decoder when high. When decoder is disabled, new commands are ignored but previous
operations continue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the
operations to be executed by the SDRAM.
Bank Address define to which bank an Activate, Read, Write or Precharge command is
being applied. Bank address also determines if the Mode Register or Extended Mode
Register is to be accessed during a MRS or EMRS cycle.
119 SDA
Pin
No.
111 DQ57
112 V
113 DQS7#
114 DQS7
115 V
116 DQ58
117 DQ59
118 V
120 SCL
Pin
Name
SS
SS
SS
Pin
No.
141 DQ15
142 V
143 DQ20
144 DQ21
145 V
146 DM2
147 NC
148 V
149 DQ22
150 DQ23
Pin
Name
SS
SS
SS
SG2567UDR212851UU
Pin
No.
171 CKE1
172 V
173 A15 (NC)
174 A14 (NC)
175 V
176 A12
177 A9
178 V
179 A8
180 A6
Pin
Name
DD
DDQ
DD
Pin
No.
201 V
202 DM4
203 NC
204 V
205 DQ38
206 DQ39
207 V
208 DQ44
209 DQ45
210 V
Pin
Name
SS
SS
SS
SS
March 17, 2008
Pin
No.
231 V
232 DM7
233 NC
234 V
235 DQ62
236 DQ63
237 V
238 V
239 SA0
240 SA1
Pin
Name
SS
SS
SS
DDSPD
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