sg2567udr212851hc ETC-unknow, sg2567udr212851hc Datasheet - Page 22
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sg2567udr212851hc
Manufacturer Part Number
sg2567udr212851hc
Description
Dram Module Ddr2 Sdram 2gbyte 240udimm
Manufacturer
ETC-unknow
Datasheet
1.SG2567UDR212851HC.pdf
(26 pages)
Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
Parameter
Clock cycle time
Clock high-level width
Clock low-level width
Clock half period
DQ output access time from CK/CK#
Data-out high-impedence window from CK/CK#
Data-out low-impedence window from CK/CK#
DQ & DM input setup time relative to DQS
DQ & DM input hold time relative to DQS
DQ & DM input pulse width (for each input)
Data hold skew factor
DQ-DQS hold, DQS to first DQ to go nonvalid, per
access
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
DQS-DQ skew, DQS to last DQ valid, per group, per
access
DQS read preamble
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
Write command to first DQS latching transition
Address & control input pulse width for each input
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
OCD Drive mode delay
CKE low to CK,CK# uncertainity
Device AC Operating Conditions
CL=5.0
CL=4.0
CL=5.0
CL=4.0
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
CH
CL
HP
AC
HZ
LZ
DS
DH
DIPW
QHS
QH
DQSH
DQSL
DQSCK
DSS
DSH
DQSQ
RPRE
RPST
WPRES
WPRE
WPST
DQSS
IPW
IS
IH
CCD
OIT
DELAY
Min
2500
3750
0.45
0.45
Min
(t
-400
-500
-
t
50
125
0.35
-
t
0.35
0.35
-350
0.2
0.2
-
0.9
0.4
0
0.35
0.4
WL - 0.25
0.6
175
250
2
0
2.925
AC
HP
CL
(min)
, t
- t
CH
QHS
2.5ns @ CL 5.0
DDR2-800-555
)
Max
8000
8000
0.55
0.55
-
+400
+500
t
t
-
-
-
300
-
-
-
+350
-
-
200
1.1
0.6
-
-
0.6
WL + 0.25
-
-
-
-
12
2.925
AC
AC
SG2567UDR212851UU
(max)
(max)
Unit
ps
ps
t
t
ps
ps
ps
ps
ps
ps
ps
t
ps
ps
t
t
ps
t
t
ps
t
t
ps
t
t
t
t
ps
ps
t
ns
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Notes
12, 20
12, 20
14
14
15
4, 5
4, 6
3, 11, 17
3, 11, 17
11,13
11,13
18
8, 9
7
2, 17
2, 17
24
March 17, 2008
22