fs6131 AMI Semiconductor, Inc., fs6131 Datasheet - Page 42

• Manufacturer Part Number: fs6131
• Description: Fs6131-01g Programmable Line Lock Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
The goal is to choose the highest crystal frequency from Table 10 that generates the smallest value of N
The equation establishing the output frequency (f
where N
Choose a few different crystal frequencies from Table 10 and factor both the input VCXO and output clock frequencies into prime
numbers. Look for the factors that will give the smallest modulus for N
reduced factors from Eqn. 1 are in Table 22.
Table 22: Clock Regenerator Example
A 19.44MHz crystal provides the smallest modulus for N
Finally, choose a post divider (N
be calculated by
Selecting an overall modulus of N
15.2 Example Programming
To generate a de-jittered output frequency of 51.84MHz from an 8kHz reference, program the following (refer to Figure 28):
• Program the VCXO control ROM to 3 via XLROM[2:0] to select an external 19.44MHz crystal
• Enable the VCXO fine tune via XLVTEN=1
• Enable the crystal loop PFD via XLPDEN=0 and XLSWAP=0
• Set the reference divider input to select the VCXO via REFDSRC
• Set the PFD input to select the reference divider and the feedback divider via PDREF and PDFBK
• Set the reference divider (N
• Set the feedback divider input to select the VCO via FBKDSRC
• Set the feedback divider (N
• Set N
• Select the internal loop filter via EXTLF
• Set VCOSPD=0 to select the VCO high speed range
These settings provide the highest frequency at the main loop phase frequency detector of 6.48MHz. The use of a 19.44MHz crystal
requires that XLROM[2:0] be set to three as shown in Table 10.
AMI Semiconductor
www.amis.com
P1
F
=1, N
is the feedback divider modulus.
P2
=3 and N
Specifications subject to change without notice
– Rev. 3.0, Jan. 08
P3
=1 for a combined post divider modulus of N
F
R
) to a modulus of 8 via FBKDIV[14:0]
) to a modulus of 3 via REFDIV[11:0]
Px
) modulus that keeps the VCO frequency in its most comfortable range. The VCO frequency (f
Px
=3 sets the VCO frequency at 155.52MHz when the loop is locked.
CLK
) as a function of the input VCXO frequency is
R
(N
R
f
=3) with the highest crystal frequency.
VCO
f
f
VCXO
CLK
42
=
f
=
CLK
R
Px
N
N
with the largest F
=3 via POST1[1:0], POST2[1:0] and POST3[1:0].
N
F
R
Px
VCXO
. The output and VCXO frequencies and the
R
.
Data Sheet
VCO
) can