fs6131 AMI Semiconductor, Inc., fs6131 Datasheet - Page 41

• Manufacturer Part Number: fs6131
• Description: Fs6131-01g Programmable Line Lock Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
15.0 Device Application: Telecom Clock Regenerator
The FS6131 can be used as a clock regenerator as shown in Figure 28. This mode uses the VCXO in its own phase-locked loop,
referred to as the crystal loop. The VCXO provides a "de-jittered" multiple of the reference frequency at the REF pin (usually 8kHz in
telecom applications) for use by the main loop. In essence, the crystal loop "cleans up" the reference signal for the main loop.
The control ROM for the VCXO divider is preloaded with the most common ratios to permit locking of most standard
telecommunications crystals to an 8kHz signal applied to the REF pin. The de-jittered multiple of the reference frequency from the
VCXO is then supplied to the reference divider in the main loop. The reference divider, along with the feedback divider, can be
programmed to achieve the desired output clock frequency.
15.1 Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters.
In this example, an 8kHz reference frequency is supplied to the FS6131 and an output clock frequency of 51.84MHz is desired.
First, select the frequency at which the VCXO will operate from Table 10. The table shows the external crystal frequency options
available to choose from, since the VCXO runs at the crystal frequency. While the main loop can be programmed to work with any of
the frequencies in the table, the best performance will be achieved with the highest frequency at the main loop PFD.
The frequency at the main loop PFD (f
AMI Semiconductor
www.amis.com
(typical)
8kHz IN
(optional)
XOUT
FBK
SDA
REF
SCL
XTUNE
(optional)
XIN
ADDR
Specifications subject to change without notice
– Rev. 3.0, Jan. 08
REFDSRC
Interface
(f
REF
VCXO
I
2
)
C
XCT[3:0],
XLVTEN
Reference
REFDIV[11:0]
Divider
(N
R
)
MLpfd
Registers
Control
Divider
VCXO
ROM
) is the VCXO frequency (f
PDREF
PDFBK
Figure 28: Block Diagram: Telecom Clock Generator
Frequency
XLROM[2:0]
Detector
Phase-
Frequency
Detector
Phase-
XLPDEN,
XLSWAP
Divider
Feedback
FBKDIV[14:0]
f
DOWN
UP
(N
MLpfd
CRYSTAL LOOP
Charge
MLCP[1:0]
Pump
F
)
41
DOWN
UP
=
Charge
XLCP[1:0]
Pump
VCXO
FBKDSRC[1:0]
f
N
VCXO
) divided by the main loop reference divider (N
Controlled
Oscillator
Voltage
R
OSCTYPE
VCOSPD,
(f
VCO
OM[1:0]
)
MAIN LOOP
Gobbler
EXTLF
Clock
GBL
Internal
Loop
Filter
LFTC
POST3[1:0],
POST2[1:0],
POST1[1:0]
Divider
(N
Post
Px
)
Detect
STAT[1:0]
FS6131
Lock
CMOS/PECL
Output
CMOS
R
).
C
R
LF
LF
C
EXTLF
(optional)
LOCK/
IPRG
(optional)
CLKP
CLKN
LP
R
(f
IPRG
CLK
)
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