fs6131 AMI Semiconductor, Inc., fs6131 Datasheet - Page 30

• Manufacturer Part Number: fs6131
• Description: Fs6131-01g Programmable Line Lock Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
10.2.1 Device Mode
The device mode block presets the demo program to program the FS6131 either as a frequency synthesizer (a stand alone clock
generator) or as a line-locked or genlock clock generator.
Frequency Synthesis: For use as a stand alone clock generator. Note that the reference source is the on-chip crystal oscillator, the
expected crystal frequency is 27MHz, and the voltage tune in the crystal oscillator (i.e. the VCXO) is disabled. The default output
frequency (CLK freq.) requested is 100MHz, with a maximum error of 10ppm, or about 100Hz. The output stage defaults to CMOS
mode.
Line-Locked/Genlock: For use in a line-lock or genlock application. Note that the reference source is the REF pin, and that the
expected reference frequency is 8kHz. The default output frequency requested is a 100x multiple of the reference frequency.
10.2.2 Example: Frequency Synthesizer Mode
By default the demo program assumes the FS6131 is configured as a stand alone clock generator. Note that the reference source
defaults to the on-chip crystal oscillator, the expected crystal frequency is 27MHz, and the voltage tune in the Crystal Oscillator block
(i.e. the VCXO) is disabled. The default output frequency (CLK freq.) requested is 100MHz, with a maximum error of 10ppm, or about
100Hz. The Output Stage defaults to CMOS mode. The Loop Filter block is set to internal, and the Check Loop Stability switch is
on.
As an exercise, click on Calculate Solutions. The program takes into account all of the screen settings and calculates all possible
combinations of reference, feedback and post divider values that will generate the output frequency (100MHz) from the input frequency
(27MHz) within the desired tolerance (10ppm).
A box will momentarily appear: "Calculating Solutions: Press cancel to stop with the solutions calculated so far." A number in the box
will increment for every unique solution that is found. This example will create seven unique solutions, which are then displayed in a
window in the lower right portion of the program screen.
The best PLL performance is obtained by running the VCO at as high a speed as possible. The last three solutions show a VCO speed
of 200MHz. Furthermore, good PLL performance is obtained with the smallest dividers possible, which means solution #4 should
provide the best results.
Clicking on Solution #4 highlights the row, and clicking on Disp/Save Register Values provides a window with the final values of key
settings. A click on OK then displays a second window containing register information per the register map. If the solutions are to be
saved to a file, two formats are available: a text format for viewing, and a data format for loading into the FS6131.
Note: As an update to this data sheet, the FS6131 hardware is no longer available from AMIS.
AMI Semiconductor
www.amis.com
Specifications subject to change without notice
– Rev. 3.0, Jan. 08
Figure 20: Frequency Synthesizer Screen
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Data Sheet