sam4s8c ATMEL Corporation, sam4s8c Datasheet - Page 35

• Manufacturer Part Number: sam4s8c
• Description: At91sam Arm-based Flash Mcu
• Manufacturer: ATMEL Corporation

9.1.3.10
9.1.3.11
9.1.4
9.2
9.2.1
11100AS–ATARM–27-Oct-11
External Memories
Boot Strategies
Static Memory Controller
SAM-BA Boot
GPNVM Bits
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the
on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART and USB.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
The SAM4S features two GPNVM bits. These bits can be cleared or set respectively through the
commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
The Flash of the SAM4S is composed of 1024 Kbytes in a single bank.
Table 9-2.
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory
layout can be changed via GPNVM.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the
Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.
Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM.
Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default.
Setting the GPNVM Bit 2 selects bank 1, clearing it selects the boot from bank 0. Asserting
ERASE clears the GPNVM Bit 2 and thus selects the boot from bank 0 by default.
The SAM4S features one External Bus Interface to provide an interface to a wide range of exter-
nal memories and to any parallel peripheral.
• 16-Mbyte Address Space per Chip Select
• 8- bit Data Bus
• Word, Halfword, Byte Transfers
• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
GPNVMBit[#]
General-purpose Non volatile Memory Bits
0
1
Boot mode selection
Security bit
Function
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