sam4s8c ATMEL Corporation, sam4s8c Datasheet - Page 27

• Manufacturer Part Number: sam4s8c
• Description: At91sam Arm-based Flash Mcu
• Manufacturer: ATMEL Corporation

7. Processor and Architecture
7.1
7.2
7.3
7.4
11100AS–ATARM–27-Oct-11
ARM Cortex-M4 Processor
APB/AHB bridge
Matrix Masters
Matrix Slaves
The SAM4S embeds One Peripheral bridge.
The peripherals of the bridge are clocked by MCK.
The Bus Matrix of the SAM4S manages 4 masters, which means that each master can perform
an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decodings.
Table 7-1.
The Bus Matrix of the SAM4S manages 5 slaves. Each slave has its own arbiter, allowing a dif-
ferent arbitration per slave.
Table 7-2.
Master 0
Master 1
Master 2
Master 3
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store
• Three-stage pipeline
• Saturating arithmetic for signal processing
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Thumb and Debug states
• Handler and Thread modes
• Low latency ISR entry and exit
List of Bus Matrix Masters
List of Bus Matrix Slaves
Internal SRAM
Internal ROM
Internal Flash
External Bus Interface
Peripheral Bridge
Cortex-M4 Instruction/Data
Cortex-M4 System
Peripheral DMA Controller (PDC)
CRC Calculation Unit
27